Displays the brand of the processor

cpuid []leaf number] `` Retrieve CPUID information from the processor. See The documentation of CPUID for more information.

CPUID leaf values

<font face="Arial" color="#FFFFFF">0000_xxxxh<br>(standard)</font>	<font face="Arial"> </font>	<font face="Arial">0000h max + ID</font>	<font face="Arial">0001h FMS + flags</font>	<font face="Arial">0002h caches (v1)</font>	<font face="Arial">0003h PSN</font>	<font face="Arial">0004h caches (v2)</font>	<font face="Arial">0005h MON</font>	<font face="Arial">0006h power mgmt</font>	<font face="Arial">0007h flags</font>
	<font face="Arial"> </font>	<font face="Arial" color="#808080">0008h reserved</font>	<font face="Arial">0009h DCA</font>	<font face="Arial">000Ah PeMo</font>	<font face="Arial">000Bh topology</font>	<font face="Arial" color="#808080">000Ch reserved</font>	<font face="Arial">000Dh X state</font>	<font face="Arial" color="#808080">000Eh reserved</font>	<font face="Arial">000Fh PQM</font>
	<font face="Arial"> </font>	<font face="Arial">0010h PQE</font>	<font face="Arial" color="#808080">0011h reserved</font>	<font face="Arial">0012h SGX</font>	<font face="Arial" color="#808080">0013h reserved</font>	<font face="Arial">0014h PT</font>	<font face="Arial">0015h frequency</font>	<font face="Arial">0016h frequency</font>	<font face="Arial">0017h attributes</font>
	<font face="Arial"> </font>	<font face="Arial">0018h TLB</font>	<font face="Arial" color="#808080">0019h reserved</font>	<font face="Arial" color="#808080">001Ah reserved</font>	<font face="Arial">001Bh PCONFIG</font>	<font face="Arial" color="#808080">001Ch reserved</font>	<font face="Arial" color="#808080">001Dh reserved</font>	<font face="Arial" color="#808080">001Eh reserved</font>	<font face="Arial" color="#808080">001Fh reserved</font>
<font face="Arial" color="#FFFFFF">2000_xxxxh<br>(Xeon Phi)</font>	<font face="Arial"> </font>	<font face="Arial">0000h max</font>	<font face="Arial">0001h flags</font>	<font face="Arial" color="#808080">0002h reserved</font>	<font face="Arial" color="#808080">0003h reserved</font>	<font face="Arial" color="#808080">0004h reserved</font>	<font face="Arial" color="#808080">0005h reserved</font>	<font face="Arial" color="#808080">0006h reserved</font>	<font face="Arial" color="#808080">0007h reserved</font>
<font face="Arial" color="#FFFFFF">4000_xxxxh<br>(hypervisor)</font>	<font face="Arial"> </font>	<font face="Arial">0000h vendor</font>	<font face="Arial">0001h interface</font>	<font face="Arial">0002h version</font>	<font face="Arial">0003h features</font>	<font face="Arial">0004h recomm.</font>	<font face="Arial">0005h limits</font>	<font face="Arial">0006h hardware</font>	<font face="Arial" color="#808080">0007h reserved</font>
<font face="Arial" color="#FFFFFF">8000_xxxxh<br>(extended)</font>	<font face="Arial"> </font>	<font face="Arial">0000h max + ID</font>	<font face="Arial">0001h FMS + flags</font>	<font face="Arial">0002h and 0003h and 0004h processor name string</font>			<font face="Arial">0005h L1 (v1)</font>	<font face="Arial">0006h L2/L3 (v1)</font>	<font face="Arial">0007h capabilities</font>
	<font face="Arial"> </font>	<font face="Arial">0008h addr + misc</font>	<font face="Arial" color="#808080">0009h reserved</font>	<font face="Arial">000Ah SVM</font>	<font face="Arial" color="#808080">000Bh reserved</font>	<font face="Arial" color="#808080">000Ch reserved</font>	<font face="Arial" color="#808080">000Dh reserved</font>	<font face="Arial" color="#808080">000Eh reserved</font>	<font face="Arial" color="#808080">000Fh reserved</font>
	<font face="Arial"> </font>	<font face="Arial" color="#808080">0010h reserved</font>	<font face="Arial" color="#808080">0011h reserved</font>	<font face="Arial" color="#808080">0012h reserved</font>	<font face="Arial" color="#808080">0013h reserved</font>	<font face="Arial" color="#808080">0014h reserved</font>	<font face="Arial" color="#808080">0015h reserved</font>	<font face="Arial" color="#808080">0016h reserved</font>	<font face="Arial" color="#808080">0017h reserved</font>
	<font face="Arial"> </font>	<font face="Arial" color="#808080">0018h reserved</font>	<font face="Arial">0019h 1G TLB</font>	<font face="Arial">001Ah perf hints</font>	<font face="Arial">001Bh IBS</font>	<font face="Arial">001Ch LWP</font>	<font face="Arial">001Dh caches (v2)</font>	<font face="Arial">001Eh topology</font>	<font face="Arial">001Fh SME/SEV</font>
<font face="Arial" color="#FFFFFF">8086_xxxxh<br>(Transmeta)</font>	<font face="Arial"> </font>	<font face="Arial">0000h max + ID</font>	<font face="Arial">0001h FMS + flags</font>	<font face="Arial">0002h HW/SW rev</font>	<font face="Arial">0003h and 0004h and 0005h and 0006h CMS info string</font>				<font face="Arial">0007h MHz + mV</font>
<font face="Arial" color="#FFFFFF">C000_xxxxh<br>(Centaur)</font>	<font face="Arial"> </font>	<font face="Arial">0000h max + ID</font>	<font face="Arial">0001h FMS + flags</font>	<font face="Arial" color="#808080">0002h reserved</font>	<font face="Arial" color="#808080">0003h reserved</font>	<font face="Arial" color="#808080">0004h reserved</font>	<font face="Arial" color="#808080">0005h reserved</font>	<font face="Arial" color="#808080">0006h reserved</font>	<font face="Arial" color="#808080">0007h reserved</font>

standard level 0000_0000h

input

EAX=0000_0000h

get maximum supported standard level and vendor ID string

output

EAX=xxxx_xxxxh

maximum supported standard level ^#1

EBX-EDX-ECX

vendor ID string ^#2

GenuineIntel

Intel processor

UMC UMC UMC

UMC processor

AuthenticAMD

AMD processor

CyrixInstead

Cyrix processor

NexGenDriven

NexGen processor

CentaurHauls

Centaur processor

RiseRiseRise

Rise Technology processor

SiS SiS SiS

SiS processor

GenuineTMx86

Transmeta processor

Geode by NSC

National Semiconductor processor

notes

descriptions

#1

According to [1] and [2] the pre-B0 step Intel P5 processors return EAX=0000_05xxh.

#2

According to [1] and [2] the pre-B0 step Intel P5 processors don't return a vendor ID string.

standard level 0000_0001h

input

EAX=0000_0001h

get processor type/family/model/stepping and feature flags

output

EAX=xxxx_xxxxh

processor type/family/model/stepping

extended family
(add)

The extended processor family is encoded in bits 27...20.

00+F

Intel P4
AMD K8 (Fam 08h)
Transmeta Efficeon

01+F

AMD K8L (Fam 10h)
Intel Itanium 2 (IA-64)

02+F

AMD K8 (Fam 11h)

03+F

AMD K8L (Fam 12h)

05+F

AMD BC (Fam 14h)

06+F

AMD BD (Fam 15h)

07+F

AMD JG (Fam 16h)

08+F

AMD ZN (Fam 17h)

02+0

Intel Itanium 2 DC (IA-64)
Intel Itanium 2 QC (IA-64)

02+1

Intel Itanium 2 8C (IA-64)

extended model
(concat)

The extended processor model is encoded in bits 19...16.

AMD K8

0

130 nm Rev C

1

90 nm Rev D

2

90 nm Rev E

4

90 nm Rev F

5

90 nm Rev F

6

65 nm Rev G

7

65 nm Rev G

C

90 nm Rev F (in Fr3)

AMD Fam 15h

0

OR

1

TN/RL

3

KV/GV

6

CZ/BR

7

ST

AMD Fam 16h

0

KB/BV

3

ML

6

NL

AMD Fam 17h

0

ZP

1

RV

Intel

1...F

see model (below)

type

The processor type is encoded in bit 13 and bit 12.

11b

reserved

10b

secondary processor (for MP)

01b

Overdrive processor

00b

primary processor

family

The family is encoded in bits 11...8.

4

most 80486s
AMD 5x86
Cyrix 5x86

5

Intel P5, P54C, P55C, P24T
Intel Quark X1000
NexGen Nx586
Cyrix M1
Cyrix MediaGX
Geode
AMD K5, K6
Centaur C6, C2, C3
Rise mP6
SiS 55x
Transmeta Crusoe

6

Intel P6, P2, P3, PM, Core 2
Intel Atom
Intel Xeon Phi (KNL)
AMD K7
Cyrix M2
VIA C3

7

Intel Itanium (IA-64)

B

Intel Xeon Phi (KNF and KNC)

F

refer to extended family

0

refer to extended family

model

The model is encoded in bits 7...4.

Intel 80486

0

i80486DX-25/33

1

i80486DX-50

2

i80486SX

3

i80486DX2

4

i80486SL

5

i80486SX2

7

i80486DX2WB

8

i80486DX4

9

i80486DX4WB

UMC 80486

1

U5D

2

U5S

AMD 80486

3

80486DX2

7

80486DX2WB

8

80486DX4

9

80486DX4WB

A

Elan SC400

E

5x86

F

5x86WB

Cyrix 5x86

9

5x86

Cyrix MediaGX

4

GX, GXm

Intel P5-core

0

P5 A-step

1

P5

2

P54C

3

P24T Overdrive

4

P55C

7

P54C

8

P55C (0.25µm)

Intel Quark

9

X1000

NexGen Nx586

0

Nx586 or Nx586FPU (only later ones)

Cyrix M1

2

6x86

Cyrix M2

0

6x86MX

Geode

4

GX1, GXLV, GXm

5

GX2

A

LX

AMD K5

0

SSA5 (PR75, PR90, PR100)

1

5k86 (PR120, PR133)

2

5k86 (PR166)

3

5k86 (PR200)

AMD K6

6

K6 (0.30 µm)

7

K6 (0.25 µm)

8

K6-2

9

K6-III

D

K6-2+ or K6-III+ (0.18 µm)

Centaur

4

C6

8

C2

9

C3

VIA C3

5

Cyrix M2 core

6

WinChip C5A core

7

WinChip C5B core (if stepping = 0...7)

7

WinChip C5C core (if stepping = 8...F)

8

WinChip C5N core (if stepping = 0...7)

9

WinChip C5XL core (if stepping = 0...7)

9

WinChip C5P core (if stepping = 8...F)

10

WinChip C5J core

Rise

0

mP6 (0.25 µm)

2

mP6 (0.18 µm)

SiS

0

55x

Transmeta Crusoe

4

TM3x00 and TM5x00

Intel P6-core

0

P6 A-step

1

P6

3

P2 (0.28 µm)

5

P2 (0.25 µm)

6

P2 with on-die L2 cache

7

P3 (0.25 µm)

8

P3 (0.18 µm) with 256 KB on-die L2

A

P3 (0.18 µm) with 2 MB on-die L2

B

P3 (0.13 µm) with 512 KB on-die L2

9

PM (0.13 µm) with 1 MB on-die L2 (Banias)

D

PM (0.09 µm) with 2 MB on-die L2 (Dothan)

E

PM DC (65 nm) with 2 MB on-die L2 (Yonah)

15

EP80579 (65 nm) with 256 KB on-die L2 (Tolapai)

F

Core 2 2C (65 nm) 4 MB L2 (Merom)

16

Core 2 1C (65 nm) 1 MB L2 (Merom-L)

17

Core 2 2C (45 nm) 6 MB L2 (Penryn)

1D

Core 2 6C (45 nm) 3x3 MB L2 + 16 MB L3 (DUN)

1A

Core 7 4C (45 nm) 8 MB L3 QPI (NHM)

1E

Core 7 4C (45 nm) 8 MB L3 PCIe (CFD/LFD/JSF)

1F

Core 7 2C (45 nm) 4 MB L3 GFX (ABD/HVD)

2E

Core 7 8C (45 nm) 24 MB L3 QPI (BEC)

2C

Core 7 6C (32 nm) 12 MB L3 QPI (WSM)

25

Core 7 2C (32 nm) 4 MB L3 GFX (ARD/CLD)

2F

Core 7 10C (32 nm) 30 MB L3 QPI (WSM-EX)

2A

Core 7 4C (32 nm) 8 MB L3 GPU (SNB-DT)

2D

Core 7 8C (32 nm) 20 MB L3 PCIe (SNB-E[NPX])

3A

Core 7 4C (22 nm) 8 MB L3 GPU (IVB-DT)

3E

Core 7 15C (22 nm) 37.5 MB L3 PCIe (IVB-E[NPX])

3C

Core 7 4C (22 nm) 8 MB L3 GPU (HSW-DT)

3F

Core 7 18C (22 nm) 45 MB L3 PCIe (HSW-E[NPX])

45

HSW low power

46

HSW Crystalwell (4C 6M GPU and 128M eDRAM)

3D

Core 7 2C (14 nm) 4 MB L3 GPU (BDW-DT)

4F

Core 7 24C (14 nm) 60 MB L3 PCIe (BDW-E[NPX])

56

Core 7 8C (14 nm) 12 MB L3 SoC (BDW-DE)

47

BDW Brystalwell (4C 6M GPU and 128M eDRAM)

4E

SKL Y/U

5E

SKL S/H

8E

KBL Y/U

9E

KBL S/H

??

CFL Y/U

??

CFL S/H

??

WHL Y/U

??

WHL S/H

55

SKX

66

CNL Y/U

??

CNL S/H

??

ICL Y/U

??

ICL S/H

??

TGL

??

ADL

Intel Atom

1C

Atom (45 nm) with 512 KB on-die L2

26

Atom (45 nm) with 512 KB on-die L2

36

Atom (32 nm) with 512 KB on-die L2

27

Atom (32 nm) with 512 KB on-die L2

35

Atom (?? nm) with ??? KB on-die L2

4A

Atom 2C (22 nm) 1 MB L2 + PowerVR (TGR)

5A

Atom 4C (22 nm) 2 MB L2 + PowerVR (ANN)

37

Atom 4C (22 nm) 2 MB L2 + Intel Gen7 (BYT)

4C

Atom 4C (14 nm) 2 MB L2 + Intel Gen8 (BSW)

5C

Atom 4C (14 nm) 2 MB L2 + Intel Gen9 (APL)

7A

Atom 4C (14 nm) 2 MB L2 + Intel Gen9 (GLK)

5D

Atom 4C (28 nm TSMC) 1 MB L2 + Mali (SoFIA)

Intel Atom

4D

Atom 8C (22 nm) 4 MB L2 (AVN)

5F

Atom 16C (14 nm) 16 MB L2 (DVN)

AMD K7

1

Athlon (0.25 µm)

2

Athlon (0.18 µm)

3

Duron (SF core)

4

Athlon (TB core)

6

Athlon (PM core)

7

Duron (MG core)

8

Athlon (TH/AP core)

A

Athlon (BT core)

AMD K8 (Fam 08h)

xx00b

Socket 754 or Socket S1

xx01b

Socket 940 or Socket F1207

xx10b

if Rev CG, then see K8 erratum #108

xx11b

Socket 939 or Socket AM2 or ASB1

01xxb

SH (SC 1024 KB)

11xxb

DH (SC 512 KB)

10xxb

CH (SC 256 KB)

00xxb

JH (DC 1024 KB)

10xxb

BH (DC 512 KB)

AMD K8L (Fam 10h)

0

Rev A DR (0/1/2=A0/A1/A2)

2

Rev B DR (0/1/A/2/3=B0/B1/BA/B2/B3)

4/5/6

Rev C RB/BL/DA (0/1/2/3=C0/C1/C2/C3)

8/9

Rev D HY SCM/MCM (0/1=D0/D1)

A

Rev E PH (0=E0)

AMD K8 (Fam 11h)

3

Rev B LG (1=B1)

AMD K8L (Fam 12h)

0

Rev A LN1 (0/1=A0/A1)

1

Rev B LN1 (0=B0)

2

Rev B LN2 (0=B0)

AMD BC (Fam 14h)

1

Rev B ON (0=B0)

2

Rev C ON (0=C0)

AMD BD (Fam 15h)

00

Rev A OR (0/1=A0/A1)

01

Rev B OR (0/1/2=B0/B1/B2)

02

Rev C OR (0=C0)

10

Rev A TN (1=A1)

13

Rev A RL (1=A1)

30

Rev A KV (0/1=A0/A1)

38

Rev A GV (1=A1)

60

Rev A CZ (0/1=A0/A1)

65

OSVW.ID5=0: Rev A CZ DDR4 (1=A1)
OSVW.ID5=1: Rev A BR (1=A1)

70

Rev A ST (0=A0)

AMD JG (Fam 16h)

00

Rev A KB (0/1=A0/A1)

04

Rev A BV (1=A1)

30

Rev A ML (0/1=A0/A1)

60

Rev A NL (1=A1)

AMD ZN (Fam 17h)

00

Rev A ZP (1=A1)

10

Rev A RV (1=A1)

Intel P4-core

0

P4 (0.18 µm)

1

P4 (0.18 µm)

2

P4 (0.13 µm)

3

P4 (0.09 µm)

4

P4 (0.09 µm)

6

P4 (65 nm)

Intel Xeon Phi

?

32C (45 nm) 8 MB L2 (KNF) (L1OM)

1

62C (22 nm) 31 MB L2 (KNC) (K1OM)

57

72C (14 nm) 36 MB L2 (KNL) (AVX512)

85

72C (14 nm) 36 MB L2 (KNM) (AVX512+)

??

??C (10 nm) ?? MB L2 (KNH)

Transmeta Efficeon

2

TM8000 (130 nm)

2

TM8000 (90 nm CMS 6.0)

3

TM8000 (90 nm CMS 6.1+)

Intel Itanium

0

Merced (180 nm)

Intel Itanium 2

0

McKinley (180 nm)

1

Madison or Deerfield (130 nm)

2

Madison 9M (130 nm)

Intel Itanium 2 DC

0

Montecito (90 nm, 9000 series)

1

Montvale (90 nm, 9100 series)

Intel Itanium 2 QC

2

Tukwila (65 nm, 9300 series)

Intel Itanium 2 8C

0

Poulson (32 nm, 9500 series)

stepping

The stepping is encoded in bits 3...0.

The stepping values are processor-specific.

EBX=aall_ccbbh

brand ID

The brand ID is encoded in bits 7...0.

00h

not supported

01h

0.18 µm Intel Celeron

02h

0.18 µm Intel Pentium III

03h

0.18 µm Intel Pentium III Xeon

03h

0.13 µm Intel Celeron

04h

0.13 µm Intel Pentium III

07h

0.13 µm Intel Celeron mobile

06h

0.13 µm Intel Pentium III mobile

0Ah

0.18 µm Intel Celeron 4

08h

0.18 µm Intel Pentium 4

09h

0.13 µm Intel Pentium 4

0Eh

0.18 µm Intel Pentium 4 Xeon

0Bh

0.18 µm Intel Pentium 4 Xeon MP

0Bh

0.13 µm Intel Pentium 4 Xeon

0Ch

0.13 µm Intel Pentium 4 Xeon MP

08h

0.13 µm Intel Celeron 4 mobile (0F24h)

0Fh

0.13 µm Intel Celeron 4 mobile (0F27h)

0Eh

0.13 µm Intel Pentium 4 mobile (production)

0Fh

0.13 µm Intel Pentium 4 mobile (samples)

11h

mobile Intel ??? processor

12h

0.13 µm Intel Celeron M

12h

0.09 µm Intel Celeron M

13h

mobile Intel Celeron ? processor

14h

Intel Celeron ? processor

15h

mobile Intel ??? processor

16h

0.13 µm Intel Pentium M

16h

0.09 µm Intel Pentium M

17h

mobile Intel Celeron ? processr

AMD

see extended level 8000_0001h
with ID=0000_0765_0000_0000b and NN=4_3210b

CLFLUSH

The CLFLUSH (8-byte) chunk count is encoded in bits 15...8.

CPU count

The logical processor count is encoded in bits 23...16.

APIC ID

The (fixed) default APIC ID is encoded in bits 31...24.

ECX=xxxx_xxxxh

feature flags

description

bit 31 (HV)

hypervisor present (and intercepting this bit, to advertise its presence)

bit 30 (RDRAND)

RDRAND

bit 29 (F16C)

VCVTPH2PS and VCVTPS2PH

bit 28 (AVX)

AVX

bit 27 (OSXSAVE)

non-privileged read-only copy of current CR4.OSXSAVE value

bit 26 (XSAVE)

CR4.OSXSAVE, XCRn, XGETBV, XSETBV, XSAVE(OPT), XRSTOR
also see standard level 0000_000Dh

bit 25 (AES)

AES*

bit 24 (TSCD)

local APIC supports one-shot operation using TSC deadline value

bit 23 (POPCNT)

POPCNT

bit 22 (MOVBE)

MOVBE

bit 21 (x2APIC)

x2APIC, APIC_BASE.EXTD, MSRs 0000_0800h...0000_0BFFh
64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF_IPI (+040h)
also see standard level 0000_000Bh

bit 20 (SSE4.2)

SSE4.2

bit 19 (SSE4.1)

SSE4.1, MXCSR, CR4.OSXMMEXCPT, #XF

bit 18 (DCA)

Direct Cache Access (that is, the ability to prefetch data from MMIO)
also see standard level 0000_0009h

bit 17 (PCID)

CR4.PCIDE

bit 16

reserved

bit 15 (PDCM)

Performance Debug Capability MSR

bit 14 (ETPRD)

MISC_ENABLE.ETPRD

bit 13 (CX16)

CMPXCHG16B

bit 12 (FMA)

FMA

bit 11 (SDBG)

DEBUG_INTERFACE MSR for silicon debug

bit 10 (CID)

context ID: the L1 data cache can be set to adaptive or shared mode
MISC_ENABLE.L1DCCM

bit 9 (SSSE3)

SSSE3

bit 8 (TM2)

MISC_ENABLE.TM2E
THERM_INTERRUPT and THERM_STATUS MSRs
xAPIC thermal LVT entry
THERM2_CONTROL MSR

bit 7 (EST)

Enhanced SpeedStep Technology

bit 6 (SMX)

CR4.SMXE, GETSEC

bit 5 (VMX)

CR4.VMXE, VM* and VM*

bit 4 (DSCPL)

CPL-qualified Debug Store

bit 3 (MON)

MONITOR/MWAIT, MISC_ENABLE.MONE, MISC_ENABLE.LCMV
MONITOR_FILTER_LINE_SIZE MSR
also see standard level 0000_0005h
setting MISC_ENABLE.MONE=0 causes MON=0

bit 2 (DTES64)

64-bit Debug Trace and EMON Store MSRs

bit 1 (PCLMUL)

PCLMULQDQ

bit 0 (SSE3)

SSE3, MXCSR, CR4.OSXMMEXCPT, #XF, if FPU=1 then also FISTTP

EDX=xxxx_xxxxh

feature flags

description

bit 31 (PBE)

Pending Break Event, STPCLK, FERR#, MISC_ENABLE.PBE

bit 30 (IA-64)

IA-64, JMPE Jv, JMPE Ev

bit 29 (TM1)

MISC_ENABLE.TM1E
THERM_INTERRUPT and THERM_STATUS MSRs
xAPIC thermal LVT entry

bit 28 (HTT)

Hyper-Threading Technology, PAUSE

bit 27 (SS)

selfsnoop

bit 26 (SSE2)

SSE2, MXCSR, CR4.OSXMMEXCPT, #XF

bit 25 (SSE)

SSE, MXCSR, CR4.OSXMMEXCPT, #XF

bit 24 (FXSR)

FXSAVE/FXRSTOR, CR4.OSFXSR

bit 23 (MMX)

MMX

bit 22 (ACPI)

THERM_CONTROL MSR

bit 21 (DTES)

Debug Trace and EMON Store MSRs

bit 20

reserved

bit 19 (CLFL)

CLFLUSH

bit 18 (PSN)

PSN (see standard level 0000_0003h), MISC_CTL.PSND ^#1

bit 17 (PSE36)

4 MB PDE bits 16...13, CR4.PSE

bit 16 (PAT)

PAT MSR, PDE/PTE.PAT

bit 15 (CMOV)

CMOVcc, if FPU=1 then also FCMOVcc/F(U)COMI(P)

bit 14 (MCA)

MCG_*/MCn_* MSRs, CR4.MCE, #MC

bit 13 (PGE)

PDE/PTE.G, CR4.PGE

bit 12 (MTRR)

MTRR* MSRs

bit 11 (SEP)

SYSENTER/SYSEXIT, SEP_* MSRs ^#2

bit 10

reserved

bit 9 (APIC)

APIC ^{#3, #4}

bit 8 (CX8)

CMPXCHG8B ^#5

bit 7 (MCE)

MCAR/MCTR MSRs, CR4.MCE, #MC

bit 6 (PAE)

64-bit PDPTE/PDE/PTEs, CR4.PAE

bit 5 (MSR)

MSRs, RDMSR/WRMSR

bit 4 (TSC)

TSC, RDTSC, CR4.TSD (doesn't imply MSR=1)

bit 3 (PSE)

PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb)

bit 2 (DE)

CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5

bit 1 (VME)

CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB

bit 0 (FPU)

FPU

notes

descriptions

#1

If the PSN has been disabled, then the PSN feature flag will read as 0. In addition the value for the maximum
supported standard level (reported by standard level 0000_0000h, register EAX) will be lower.

#2

The Intel P6 processor does not support SEP, but inadvertently reports it.

#3

If the APIC has been disabled, then the APIC feature flag will read as 0.

#4

Early AMD K5 processors (SSA5) inadvertently used this bit to report PGE support.

#5

Some processors do support CMPXCHG8B, but don't report it by default. This is due to a Windows NT bug.

standard level 0000_0002h

input

EAX=0000_0002h

get processor configuration descriptors

output

AL

number of times this level must be queried to obtain all configuration descriptors ^#1

EAX.15...8
EAX.23...16
EAX.31...24
EBX.0...7
EBX.15...8
EBX.23...16
EBX.31...24
ECX.0...7
ECX.15...8
ECX.23...16
ECX.31...24
EDX.0...7
EDX.15...8
EDX.23...16
EDX.31...24

configuration descriptors ^#2

value

description

00h

null descriptor (=unused descriptor)

01h

code TLB, 4K pages, 4 ways, 32 entries

02h

code TLB, 4M pages, fully, 2 entries

03h

data TLB, 4K pages, 4 ways, 64 entries

04h

data TLB, 4M pages, 4 ways, 8 entries

05h

data TLB, 4M pages, 4 ways, 32 entries

06h

code L1 cache, 8 KB, 4 ways, 32 byte lines

08h

code L1 cache, 16 KB, 4 ways, 32 byte lines

09h

code L1 cache, 32 KB, 4 ways, 64 byte lines

0Ah

data L1 cache, 8 KB, 2 ways, 32 byte lines

0Bh

code TLB, 4M pages, 4 ways, 4 entries

0Ch

data L1 cache, 16 KB, 4 ways, 32 byte lines

0Dh

data L1 cache, 16 KB, 4 ways, 64 byte lines (ECC)

0Eh

data L1 cache, 24 KB, 6 ways, 64 byte lines

10h

data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)

15h

code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)

1Ah

code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64)

1Dh

code and data L2 cache, 128 KB, 2 ways, 64 byte lines

21h

code and data L2 cache, 256 KB, 8 ways, 64 byte lines

22h

code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, dual-sectored

23h

code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored

24h

code and data L2 cache, 1024 KB, 16 ways, 64 byte lines

25h

code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored

29h

code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored

2Ch

data L1 cache, 32 KB, 8 ways, 64 byte lines

30h

code L1 cache, 32 KB, 8 ways, 64 byte lines

39h

code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored

3Ah

code and data L2 cache, 192 KB, 6 ways, 64 byte lines, sectored

3Bh

code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored

3Ch

code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored

3Dh

code and data L2 cache, 384 KB, 6 ways, 64 byte lines, sectored

3Eh

code and data L2 cache, 512 KB, 4 ways, 64 byte lines, sectored

40h

no integrated L2 cache (P6 core) or L3 cache (P4 core)

41h

code and data L2 cache, 128 KB, 4 ways, 32 byte lines

42h

code and data L2 cache, 256 KB, 4 ways, 32 byte lines

43h

code and data L2 cache, 512 KB, 4 ways, 32 byte lines

44h

code and data L2 cache, 1024 KB, 4 ways, 32 byte lines

45h

code and data L2 cache, 2048 KB, 4 ways, 32 byte lines

46h

code and data L3 cache, 4096 KB, 4 ways, 64 byte lines

47h

code and data L3 cache, 8192 KB, 8 ways, 64 byte lines

48h

code and data L2 cache, 3072 KB, 12 ways, 64 byte lines

49h

code and data L3 cache, 4096 KB, 16 ways, 64 byte lines (P4) or
code and data L2 cache, 4096 KB, 16 ways, 64 byte lines (Core 2)

4Ah

code and data L3 cache, 6144 KB, 12 ways, 64 byte lines

4Bh

code and data L3 cache, 8192 KB, 16 ways, 64 byte lines

4Ch

code and data L3 cache, 12288 KB, 12 ways, 64 byte lines

4Dh

code and data L3 cache, 16384 KB, 16 ways, 64 byte lines

4Eh

code and data L2 cache, 6144 KB, 24 ways, 64 byte lines

4Fh

code TLB, 4K pages, ???, 32 entries

50h

code TLB, 4K/4M/2M pages, fully, 64 entries

51h

code TLB, 4K/4M/2M pages, fully, 128 entries

52h

code TLB, 4K/4M/2M pages, fully, 256 entries

55h

code TLB, 2M/4M, fully, 7 entries

56h

L0 data TLB, 4M pages, 4 ways, 16 entries

57h

L0 data TLB, 4K pages, 4 ways, 16 entries

59h

L0 data TLB, 4K pages, fully, 16 entries

5Ah

L0 data TLB, 2M/4M, 4 ways, 32 entries

5Bh

data TLB, 4K/4M pages, fully, 64 entries

5Ch

data TLB, 4K/4M pages, fully, 128 entries

5Dh

data TLB, 4K/4M pages, fully, 256 entries

60h

data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored

61h

code TLB, 4K pages, fully, 48 entries

63h

data TLB, 2M/4M pages, 4-way, 32-entries, and
data TLB, 1G pages, 4-way, 4 entries

64h

data TLB, 4K pages, 4-way, 512 entries

66h

data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored

67h

data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored

68h

data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored

6Ah

L0 data TLB, 4K pages, 8-way, 64 entries

6Bh

data TLB, 4K pages, 8-way, 256 entries

6Ch

data TLB, 2M/4M pages, 8-way, 126 entries

6Dh

data TLB, 1G pages, fully, 16 entries

70h

trace L1 cache, 12 KµOPs, 8 ways

71h

trace L1 cache, 16 KµOPs, 8 ways

72h

trace L1 cache, 32 KµOPs, 8 ways

73h

trace L1 cache, 64 KµOPs, 8 ways

76h

code TLB, 2M/4M pages, fully, 8 entries

77h

code L1 cache, 16 KB, 4 ways, 64 byte lines, sectored (IA-64)

78h

code and data L2 cache, 1024 KB, 4 ways, 64 byte lines

79h

code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored

7Ah

code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored

7Bh

code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectored

7Ch

code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored

7Dh

code and data L2 cache, 2048 KB, 8 ways, 64 byte lines

7Eh

code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64)

7Fh

code and data L2 cache, 512 KB, 2 ways, 64 byte lines

80h

code and data L2 cache, 512 KB, 8 ways, 64 byte lines

81h

code and data L2 cache, 128 KB, 8 ways, 32 byte lines

82h

code and data L2 cache, 256 KB, 8 ways, 32 byte lines

83h

code and data L2 cache, 512 KB, 8 ways, 32 byte lines

84h

code and data L2 cache, 1024 KB, 8 ways, 32 byte lines

85h

code and data L2 cache, 2048 KB, 8 ways, 32 byte lines

86h

code and data L2 cache, 512 KB, 4 ways, 64 byte lines

87h

code and data L2 cache, 1024 KB, 8 ways, 64 byte lines

88h

code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64)

89h

code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64)

8Ah

code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64)

8Dh

code and data L3 cache, 3072 KB, 12 ways, 128 byte lines (IA-64)

90h

code TLB, 4K...256M pages, fully, 64 entries (IA-64)

96h

data L1 TLB, 4K...256M pages, fully, 32 entries (IA-64)

9Bh

data L2 TLB, 4K...256M pages, fully, 96 entries (IA-64)

A0h

data TLB, 4K pages, fully, 32 entries

B0h

code TLB, 4K pages, 4 ways, 128 entries

B1h

code TLB, 4M pages, 4 ways, 4 entries and
code TLB, 2M pages, 4 ways, 8 entries

B2h

code TLB, 4K pages, 4 ways, 64 entries

B3h

data TLB, 4K pages, 4 ways, 128 entries

B4h

data TLB, 4K pages, 4 ways, 256 entries

B5h

code TLB, 4K pages, 8 ways, 64 entries

B6h

code TLB, 4K pages, 8 ways, 128 entries

BAh

data TLB, 4K pages, 4 ways, 64 entries

C0h

data TLB, 4K/4M pages, 4 ways, 8 entries

C1h

L2 code and data TLB, 4K/2M pages, 8 ways, 1024 entries

C2h

data TLB, 2M/4M pages, 4 ways, 16 entries

C3h

L2 code and data TLB, 4K/2M pages, 6 ways, 1536 entries and
L2 code and data TLB, 1G pages, 4 ways, 16 entries

C4h

data TLB, 2M/4M pages, 4-way, 32 entries

CAh

L2 code and data TLB, 4K pages, 4 ways, 512 entries

D0h

code and data L3 cache, 512-kb, 4 ways, 64 byte lines

D1h

code and data L3 cache, 1024-kb, 4 ways, 64 byte lines

D2h

code and data L3 cache, 2048-kb, 4 ways, 64 byte lines

D6h

code and data L3 cache, 1024-kb, 8 ways, 64 byte lines

D7h

code and data L3 cache, 2048-kb, 8 ways, 64 byte lines

D8h

code and data L3 cache, 4096-kb, 8 ways, 64 byte lines

DCh

code and data L3 cache, 1536-kb, 12 ways, 64 byte lines

DDh

code and data L3 cache, 3072-kb, 12 ways, 64 byte lines

DEh

code and data L3 cache, 6144-kb, 12 ways, 64 byte lines

E2h

code and data L3 cache, 2048-kb, 16 ways, 64 byte lines

E3h

code and data L3 cache, 4096-kb, 16 ways, 64 byte lines

E4h

code and data L3 cache, 8192-kb, 16 ways, 64 byte lines

EAh

code and data L3 cache, 12288-kb, 24 ways, 64 byte lines

EBh

code and data L3 cache, 18432-kb, 24 ways, 64 byte lines

ECh

code and data L3 cache, 24576-kb, 24 ways, 64 byte lines

F0h

64 byte prefetching

F1h

128 byte prefetching

FEh

query standard level 0000_0018h instead

FFh

query standard level 0000_0004h instead

value

description

70h

Cyrix specific: code and data TLB, 4K pages, 4 ways, 32 entries

74h

Cyrix specific: ???

77h

Cyrix specific: ???

80h

Cyrix specific: code and data L1 cache, 16 KB, 4 ways, 16 byte lines

82h

Cyrix specific: ???

84h

Cyrix specific: ???

value

description

others

reserved

example (here: P6)

EAX=0302_0101h
EBX=0000_0000h
ECX=0000_0000h
EDX=0604_0A43h

Because AL is 01h, one invocation of the level is enough to obtain all the configuration descriptors. All of them are valid because their highest bits are 0. This P6 processor includes a 4K/M code/data TLB, an 8+8 KB code/data L1 cache and an integrated 512 KB code and data L2 cache.

notes

descriptions

#1

In a MP system special precautions must be taken when executing standard level 0000_0002h more than once.
In particular it must be ensured that the same CPU is used during that entire process.

#2

Programs must not expect any particular order for the reported configuration descriptors.

standard level 0000_0003h

input

EAX=0000_0003h

get processor serial number ^#1

output

EAX=xxxx_xxxxh

processor serial number (Transmeta Efficeon processors only)

EBX=xxxx_xxxxh

processor serial number (Transmeta Crusoe and Efficeon processors only)

ECX=xxxx_xxxxh

processor serial number

EDX=xxxx_xxxxh

processor serial number

note

description

#1

This level is only supported and enabled if the PSN feature flag is set. The reported processor serial number should be combined with the vendor ID string and the processor type/family/model/stepping value, to distinguish cases in which two processors from different vendors happen to have the same serial number. Finally, it should be noted that most vendors can not guarantee that their serial numbers are truely unique.

standard level 0000_0004h

input

EAX=0000_0004h

get cache configuration descriptors ^#1

ECX=xxxx_xxxxh

cache level to query (e.g. 0=L1D, 1=L2, or 0=L1D, 1=L1I, 2=L2)

output

EAX

bits

description

31...26

cores per package - 1

25...14

threads per cache - 1

13...10

reserved

9

fully associative?

8

self-initializing?

7...5

cache level (starts at 1)

4...0

cache type (0=null, 1=data, 2=code, 3=unified, 4...31=reserved)

EBX

bits

description

31...22

ways of associativity - 1

21...12

physical line partitions - 1

11...0

system coherency line size - 1

ECX

bits

description

31...0

sets - 1

EDX

bits

description

31...3

reserved

2

complex indexing?

1

inclusive of lower levels?

0

write-back invalidate?

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0005h

input

EAX=0000_0005h

get MON information ^#1

output

EAX

bits

description

31...16

reserved

15...0

smallest monitor line size in bytes

EBX

bits

description

31...16

reserved

15...0

largest monitor line size in bytes

ECX

bits

description

31...2

reserved

1

treat interrupts as break events, even when interrupts are disabled

0

enumeration of MWAIT extensions (beyond EAX and EBX)

EDX

bits

description

31...28

number of C7 sub C-states for MWAIT

27...24

number of C6 sub C-states for MWAIT

23...20

number of C5 sub C-states for MWAIT

19...16

number of C4 sub C-states for MWAIT (starting with Core 7: C7)

15...12

number of C3 sub C-states for MWAIT (starting with Core 7: C6)

11...8

number of C2 sub C-states for MWAIT

7...4

number of C1 sub C-states for MWAIT

3...0

number of C0 sub C-states for MWAIT

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0006h

input

EAX=0000_0006h

get power management information ^#1

output

EAX

bits

description

31...19

reserved

18

reserved

17

reserved

16

reserved

15

reserved

14

reserved

13 (HDC)

PKG_HDC_CTL, PM_CTL1, and THREAD_STALL MSRs

12

reserved

11 (HWP_PLR)

HWP_REQUEST_PKG MSR

10 (HWP_EPP)

HWP_REQUEST MSR bits 31...24

9 (HWP_ACT)

HWP_REQUEST MSR bits 41...32

8 (HWP_NOT)

HWP_INTERRUPT MSR

7 (HWP)

PM_ENABLE bit 0, and HWP_{CAPABILITIES,REQUEST,STATUS} MSRs

6 (PTM)

PACKAGE_THERMAL_STATUS MSR

5 (ECMD)

CLOCK_MODULATION MSR

4 (PLN)

THERM_STATUS MSR bits 10/11
THERM_INTERRUPT MSR bit 24

3

reserved

2 (ARAT)
2 (OPP)

always running APIC timer (in every C-state and regardless of P-state)
P4: operating point protection (protect CPU's ratio/VID points) ^#2

1 (DA)

dynamic acceleration (MISC.ENABLE.DAD=0)

0 (DTS)

digital thermal sensor

EBX

bits

description

31...4

reserved

3...0

number of programmable digital thermal sensor interrupt thresholds

ECX

bits

description

31...4

reserved

3

ENERGY_PERF_BIAS MSR (0000_01B0h)

2

reserved

1

ACNT2

0

MPERF/APERF

EDX

bits

description

31...0

reserved

notes

descriptions

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

#2

The implementation of OPP is processor and stepping specific.
On certain Pentium 4 processors, the protection mechanism is Snap-to-VID and it is enabled if the bit is set.

standard level 0000_0007h

input

EAX=0000_0007h

get feature flags ^#1

ECX=xxxx_xxxxh

sub-level to query (0...n as per EAX reported by sub-level 0)

output
(sub 0)

EAX

bits

description

31...0

maximum supported sub-level

EBX

bits

description

31 (AVX512VL)

AVX512VL

30 (AVX512BW)

AVX512BW

29 (SHA)

SHA

28 (AVX512CD)

AVX512CD

27 (AVX512ER)

AVX512ER

26 (AVX512PF)

AVX512PF

25 (PT)

processor trace, standard level 0000_0014h

24 (CLWB)

CLWB

23 (CLFLUSHOPT)

CLFLUSHOPT

22 (PCOMMIT)

PCOMMIT

21 (AVX512IFMA)

AVX512IFMA

20 (SMAP)

CR4.SMAP, CLAC and STAC

19 (ADX)

ADCX and ADOX

18 (RDSEED)

RDSEED

17 (AVX512DQ)

AVX512DQ

16 (AVX512F)

AVX512F, EVEX, ZMM0...31, K0...7, modifiers, VSIB512, disp8*N

15 (PQE)

platform quality of service enforcement

14 (MPX)

XCR0.Breg, XCR0.BNDCSR, BNDCFGS/BNDCFGU/BNDSTATUS and BND0...BND3, BND:, MPX

13 (FPCSDS)

FP_CS and FP_DS always saved as 0000h

12 (PQM)

platform quality of service monitoring

11 (RTM)

XBEGIN, XABORT, XEND, XTEST, DR7.RTM, DR6.RTM

10 (INVPCID)

INVPCID

9 (ERMS)

enhanced REP MOVSB/STOSB (while MISC_ENABLE.FSE=1)

8 (BMI2)

BMI2

7 (SMEP)

CR4.SMEP

6 (FPDP)

FP_DP for non-control instructions only if unmasked exception(s)

5 (AVX2)

AVX2 (including VSIB)

4 (HLE)

XACQUIRE:, XRELEASE:, XTEST

3 (BMI1)

BMI1 and TZCNT

2 (SGX)

CR4.SEE, PRMRR, ENCLS and ENCLU, standard level 0000_0012h

1 (TSC_ADJUST)

TSC_ADJUST

0 (FSGSBASE)

CR4.FSGSBASE and [RD|WR][FS|GS]BASE

ECX

bits

description

31

reserved

30 (SGX_LC)

SGX launch configuration

29

reserved

28

reserved

27

reserved

26

reserved

25

reserved

24

reserved

23

reserved

22 (RDPID)

RDPID, TSC_AUX

21 (MAWAU)

MPX address-width adjust for CPL=3

20 (MAWAU)

MPX address-width adjust for CPL=3

19 (MAWAU)

MPX address-width adjust for CPL=3

18 (MAWAU)

MPX address-width adjust for CPL=3

17 (MAWAU)

MPX address-width adjust for CPL=3

16 (VA57)

5-level paging, CR4.VA57

15

reserved

14 (AVX512VP...DQ)

VPOPCNT{D,Q}

13 (TME)

TME

12 (AVX512BITALG)

VPOPCNT{B,W} and VPSHUFBITQMB

11 (AVX512VNNI)

VPDP{BUS,WSS}D[S]

10 (VPCL)

VPCLMULQDQ (VEX.256 and EVEX)

9 (VAES)

VAES{ENC,DEC}{,LAST} (VEX.256 and EVEX)

8 (GFNI)

[V]GF2P8AFFINE{,INV}QB and [V]GF2P8MULB (SSE, VEX, and EVEX)

7 (CET)

CR4.CET, XSS.CET_{U,S}, {U,S}_CET MSRs, PL{0,1,2,3}_SSP MSRs,
IST_SSP MSR and 8-entry interrupt SSP table, #CP, SSP, TSS32.SSP,
INCSSP, RDSSP, SAVESSP, RSTORSSP, SETSSBSY, CLRSSBSY,
WRSS, WRUSS, ENDBR32, ENDBR64, CALL/JMP Rv + no track (3Eh)

6 (AVX512VBMI2)

VP{EXPAND,COMPRESS}{B,W} and VP{SHL,SHR}D{,V}{W,D,Q}

5

reserved

4 (OSPKE)

non-privileged read-only copy of current CR4.PKE value

3 (PKU)

XCR0.PKRU, CR4.PKE, PKRU, RDPKRU/WRPKRU, PxE.PK, #PF.PK

2 (UMIP)

CR4.UMIP for #GP on SGDT, SIDT, SLDT, STR, and SMSW if CPL>0

1 (AVX512VBMI)

AVX512VBMI

0 (PREFETCHWT1)

PREFETCHWT1

EDX

bits

description

31

reserved

30

reserved

29

ARCH_CAPABILITIES MSR

28

reserved

27 (STIBP)

SPEC_CTRL.STIBP

26 (IBRS_IBPB)

SPEC_CTRL.IBRS and PRED_CMD.IBPB

25

reserved

24

reserved

23

reserved

22

reserved

21

reserved

20

reserved

19

reserved

18 (PCONFIG)

PCONFIG (for MK-TME)

17

reserved

16

reserved

15

reserved

14

reserved

13

reserved

12

reserved

11

reserved

10

reserved

9

reserved

8

reserved

7

reserved

6

reserved

5

reserved

4

reserved

3 (AVX512QFMA)

V4F[N]MADD{PS,SS}

2 (AVX512QVNNIW)

VP4DPWSSD[S]

1

reserved

0

reserved

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0009h

input

EAX=0000_0009h

get DCA parameters ^#1

output

EAX

bits

description

31...0

value of PLATFORM_DCA_CAP MSR (0000_01F8h, bits 31...0)

EBX

bits

description

31...0

reserved

ECX

bits

description

31...0

reserved

EDX

bits

description

31...0

reserved

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_000Ah

input

EAX=0000_000Ah

get architectural PeMo information ^#1

output

EAX

bits

description

31...24

length of EBX bit vector

23...16

bit width of PeMo counter(s)

15...8

number of PeMo counters per logical processor

7...0

revision

EBX

bits

description

31...7

reserved

6

branch mispredicts retired event unavailable

5

branch instructions retired event unavailable

4

last level cache misses event unavailable

3

last level cache references event unavailable

2

reference cycles event unavailable

1

instructions retired event unavailable

0

core cycles event unavailable

ECX

bits

description

31...0

reserved

EDX

bits

description

31...13

reserved

12...5

bit width of fixed-function PeMo counters (if revision > 1)

4...0

number of fixed-function PeMo counters (if revision > 1)

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_000Bh

input

EAX=0000_000Bh

get topology enumeration information ^#1

ECX=0000_00xxh

sub-level to query (00h=SMT)

output

EAX

bits

description

31...5

reserved

4...0

number of bits to shift x2APIC ID right to get unique topology ID of next level type
all logical processors with same next level ID share current level

EBX

bits

description

31...16

reserved

15...0

number of enabled logical processors at this level

ECX

bits

description

31...16

reserved

15...8

level type (00h=invalid, 01h=SMT, 02h=core, 03h...FFh=reserved

7...0

level number (same as input)

EDX

bits

description

31...0

x2APIC ID of current logical processor

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_000Dh

input

EAX=0000_000Dh

get extended state enumeration ^#1

ECX=0000_00xxh

sub-level to query (0=main, 1=reserved, 2...62 as per XCR0.n)

output (main)

EAX

bits

description

31...0

valid XCR0.31...0 bits

EBX

bits

description

31...0

current size (in bytes) of XSAVE/XRSTOR area (as per current XCR0)

ECX

bits

description

31...0

max. size (in bytes) of XSAVE/XRSTOR area (incl. XSAVE.HEADER)

EDX

bits

description

31...0

valid XCR0.63...32 bits

output
(res.)

EAX

bits

description

31...4

reserved

3

XSAVES/XRSTORS and XSS

2

XGETBV with ECX=1

1

XSAVEC and compacted form of XRSTOR

0

XSAVEOPT

EBX

bits

description

31...0

size (in bytes) in XSAVE area for XCR0 | XSS

ECX

bits

description

31...0

valid XSS.31...0 bits

EDX

bits

description

31...0

valid XSS.63...32 bits

output (sub)

EAX

bits

description

31...0

size (in bytes) in XSAVE/XRSTOR area for XCR0.n (n=ECX=2...62)
0 if n was invalid

EBX

bits

description

31...0

offset (in bytes) in XSAVE/XRSTOR area for XCR0.n (n=ECX=2...62)
0 if n was invalid

ECX

bits

description

31...2

reserved

1

0 if component immediately follows previous component
1 if component is aligned to next 64 byte boundary

0

1 if n was valid in XSS
0 if n was invalid

EDX

bits

description

31...0

reserved
0 if n was invalid

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_000Fh

input

EAX=0000_000Fh

get platform quality of service monitoring (PQM) enumeration ^#1

ECX=0000_00xxh

sub-level to query (0=resources, 1...n as per EDX reported by sub-level 0)

output (main)

EAX

bits

description

31...0

reserved

EBX

bits

description

31...0

max. range (zero-based) of RMID within this phys. processor of all types

ECX

bits

description

31...0

reserved

EDX

bits

description

31...2

reserved

1

L3 cache QoS monitoring

0

reserved

output
(1=L3)

EAX

bits

description

31...0

reserved

EBX

bits

description

31...0

conversion factor from QM_CTR value to occupancy metric (bytes)

ECX

bits

description

31...0

max. range (zero-based) of RMID within this resource type

EDX

bits

description

31...3

reserved

2

L3 local external bandwidth monitoring

1

L3 total external bandwidth monitoring

0

L3 occupancy monitoring

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0010h

input

EAX=0000_0010h

get platform quality of service enforcement (PQE) enumeration ^#1

ECX=0000_00xxh

sub-level to query (0=resources, 1...n as per EBX reported by sub-level 0)

output (main)

EAX

bits

description

31...0

reserved

EBX

bits

description

31...4

reserved

3

memory bandwidth allocation

2

L2 cache QoS enforcement

1

L3 cache QoS enforcement

0

reserved

ECX

bits

description

31...0

reserved

EDX

bits

description

31...0

reserved

output
(1=L3)

EAX

bits

description

31...5

reserved

4...0

length of capacity bit mask for resource n using minus-one notation

EBX

bits

description

31...0

bit-granular map of isolation/contention of allocation units

ECX

bits

description

31...3

reserved

2

code/data prioritization – set L3_QOS_CFG MSR bit 0 to 1 to enable

1

updates of COS should be infrequent

0

reserved

EDX

bits

description

31...16

reserved

15...0

highest COS number supported for resource n

output
(2=L2)

EAX

bits

description

31...5

reserved

4...0

length of capacity bit mask for resource n using minus-one notation

EBX

bits

description

31...0

bit-granular map of isolation/contention of allocation units

ECX

bits

description

31...3

reserved

2

code/data prioritization – set L2_QOS_CFG MSR bit 0 to 1 to enable

1...0

reserved

EDX

bits

description

31...16

reserved

15...0

highest COS number supported for resource n

output
(3=M)

EAX

bits

description

31...12

reserved

11...0

maximum MBA throttling value for resource n using minus-one notation

EBX

bits

description

31...0

reserved

ECX

bits

description

31...3

reserved

2

response to delay value is linear

1...0

reserved

EDX

bits

description

31...16

reserved

15...0

highest COS number supported for resource n

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0012h

input

EAX=0000_0012h

get SGX resource enumeration ^#1

ECX=xxxx_xxxxh

sub-level to query (0=capabilities, 1=SECS, 2...n=EPC)

output
(capab.)

EAX

bits

description

31...7

reserved

6

ETRACKC/ERDINFO/ELDBC/ELDUC

5

ENCLV and EINCVIRTCHILD/EDECVIRTCHILD/ESETCONTEXT

4...2

reserved

1 (SGX2)

EAUG/EMODPR/EMODT and EACCEPT/EMODPE/EACCEPTCOPY

0 (SGX1)

ENCLS and ENCLU, #PF.SGX

EBX

bits

description

31...0

bit vector of supported extended features that can be written to SSA.MISC

ECX

bits

description

31...0

reserved

EDX

bits

description

31...16

reserved

15...8

maximum enclave size in 2^n bytes when not in PM64

7...0

maximum enclave size in 2^n bytes when in PM64

output
(SECS)

EAX

bits

description

31...0

SECS.ATTRIBUTES.31...0 that can be set with ENCLS[ECREATE]

EBX

bits

description

31...0

SECS.ATTRIBUTES.63...32 that can be set with ENCLS[ECREATE]

ECX

bits

description

31...0

SECS.ATTRIBUTES.95...64 that can be set with ENCLS[ECREATE]

EDX

bits

description

31...0

SECS.ATTRIBUTES.127...96 that can be set with ENCLS[ECREATE]

output
(EPC)

EAX

bits

description

31...12

EPC base bits 31...12

11...4

reserved

3...0

0000b = not valid, 0001b = level is valid, other = reserved

EBX

bits

description

31...20

reserved

19...0

EPC base bits 51...32

ECX

bits

description

31...12

EPC size bits 31...12

11...4

reserved

3...0

0000b = not valid, 0001b = EPC section is protected, other = reserved

EDX

bits

description

31...20

reserved

19...0

EPC size bits 51...32

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0014h

input

EAX=0000_0014h

get processor trace (PT) capability enumeration ^#1

ECX=0000_00xxh

sub-level to query (0=capabilities, 1=details – 1...31 as per EAX reported by sub-level 0)

output
(capab.)

EAX

bits

description

31...0

max sub-level

EBX

bits

description

31...6

reserved

5 (PET)

power event trace, RTIT_CTL.PwrEvtEn

4 (PTWRITE)

PTWRITE, RTIT_CTL.PTWEn, RTIT.CTL.FUPonPTW

3 (MTC)

MTC timing packet, suppression of COFI-based packets

2 (IPFILT_WRSTPRSV)

IP filtering, TraceStop filtering, PT MSR preservation across warm reset

1 (CPSB_CAM)

configurable PSB, cycle-accurate mode

0

CR3 filtering

ECX

bits

description

31 (LIP)

IP payloads are LIP

30...4

reserved

3

output to trace transport subsystem

2 (SNGLRNGOUT)

single-range output scheme

1 (MENTRY)

ToPA tables allow multiple output entries

0 (TOPAOUT)

ToPA output

EDX

bits

description

31...0

reserved

output
(details)

EAX

bits

description

31...16

bitmap of supported MTC period encodings

15...3

reserved

2...0

number of configurable address ranges for filtering

EBX

bits

description

31...16

bitmap of supported configurable PSB frequency encodings

15...0

bitmap of supported cycle threshold value encodings

ECX

bits

description

31...0

reserved

EDX

bits

description

31...0

reserved

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0015h

input

EAX=0000_0015h

get processor frequency information ^#1

output

EAX

bits

description

31...0

denominator (TSC frequency = core crystal clock frequency * EBX/EAX)

EBX

bits

description

31...0

numerator (TSC frequency = core crystal clock frequency * EBX/EAX)

ECX

bits

description

31...0

core crystal clock frequency in Hz

EDX

bits

description

31...0

reserved

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0016h

input

EAX=0000_0016h

get processor frequency information ^#1

output

EAX

bits

description

31...16

reserved

15...0

core base frequency in MHz

EBX

bits

description

31...16

reserved

15...0

core maximum frequency in MHz

ECX

bits

description

31...16

reserved

15...0

bus (reference) frequency in MHz

EDX

bits

description

31...0

reserved

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0017h

input

EAX=0000_0017h

get processor vendor attribute information ^#1

output
(main)

EAX

bits

description

31...0

max sub-level

EBX

bits

description

31...17

reserved

16

vendor ID uses industry standard enumeration scheme (0=no, 1=yes)

15...0

vendor ID

ECX

bits

description

31...0

project ID

EDX

bits

description

31...0

stepping ID

output
(1 of 3)

EAX

bits

description

31...0

UTF-8 encoded vendor brand string – part 1/12

EBX

bits

description

31...0

UTF-8 encoded vendor brand string – part 2/12

ECX

bits

description

31...0

UTF-8 encoded vendor brand string – part 3/12

EDX

bits

description

31...0

UTF-8 encoded vendor brand string – part 4/12

output
(2 of 3)

EAX

bits

description

31...0

UTF-8 encoded vendor brand string – part 5/12

EBX

bits

description

31...0

UTF-8 encoded vendor brand string – part 6/12

ECX

bits

description

31...0

UTF-8 encoded vendor brand string – part 7/12

EDX

bits

description

31...0

UTF-8 encoded vendor brand string – part 8/12

output
(3 of 3)

EAX

bits

description

31...0

UTF-8 encoded vendor brand string – part 9/12

EBX

bits

description

31...0

UTF-8 encoded vendor brand string – part 10/12

ECX

bits

description

31...0

UTF-8 encoded vendor brand string – part 11/12

EDX

bits

description

31...0

UTF-8 encoded vendor brand string – part 12/12

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0018h

input

EAX=0000_0018h

get TLB information ^#1

ECX=xxxx_xxxxh

sub-level to query (0...n as per EAX reported by sub-level 0)

output

EAX

bits

description

31...0

sub-level=0: max sub-level
sub-level>0: reserved

EBX

bits

description

31...16

ways

15...11

reserved

10...8

partitioning (0: soft between logical processors sharing this TC)

7...4

reserved

3

1G

2

4M

1

2M

0

4K

ECX

bits

description

31...0

sets

EDX

bits

description

31...26

reserved

25...14

max. number of addressable IDs for logical processors sharing this TC - 1

13...9

reserved

8

fully associative?

7...5

TC level (starts at 1)

4...0

TC type (00000b=invalid, 00001b=data, 00010b=code, 00011b=unified)

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_001Bh

input

EAX=0000_001Bh

get PCONFIG information ^#1

ECX=xxxx_xxxxh

sub-level to query (0=invalid, 1=target ID, 2...n=invalid – see EAX bits 11...0 in output)

output
(invalid)

EAX

bits

description

31...12

reserved (0)

11...0

invalid (0)

EBX

bits

description

31...0

reserved (0)

ECX

bits

description

31...0

reserved (0)

EDX

bits

description

31...0

reserved (0)

output
(target ID)

EAX

bits

description

31...12

reserved (0)

11...0

target ID (1)

EBX

bits

description

31...0

target ID 1

ECX

bits

description

31...0

target ID 2

EDX

bits

description

31...0

target ID 3

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

Intel Xeon Phi level 2000_0000h

input

EAX=2000_0000h

get maximum supported level

output

EAX=xxxx_xxxxh

maximum supported level

Intel Xeon Phi level 2000_0001h

input

EAX=2000_0001h

get processor information

output

EDX=xxxx_xxxxh

feature flags

description of indicated feature

bits 31...5

reserved

bit 4 (K1OM)

MVEX (62h), ZMM0...31, K0...7, transform modifiers, VSIB512, disp8*N

bits 3...0

reserved

hypervisor level 4000_0000h

input

EAX=4000_0000h

get hypervisor information – vendor ^#1

output

EAX

bits

description

31...0

reserved

EBX-ECX-EDX

bits

description

Microsoft Hv

Microsoft

VMwareVMware

VMware

prl hyperv

Parallels

note

description

#1

This level is only available if implemented by the hypervisor.

hypervisor level 4000_0001h

input

EAX=4000_0001h

get hypervisor information – interface ^#1

output

EAX

bits

description

31...0

interface signature (e.g. 31237648h = "Hv#1")

EBX

bits

description

31...0

reserved

ECX

bits

description

31...0

reserved

EDX

bits

description

31...0

reserved

note

description

#1

This level is only available if implemented by the hypervisor.

hypervisor level 4000_0002h

input

EAX=4000_0002h

get hypervisor information – version ^#1

output

EAX

bits

description

31...0

build number

EBX

bits

description

31...16

major version

15...0

minor version

ECX

bits

description

31...0

service pack

EDX

bits

description

31...24

service branch

23...0

service number

note

description

#1

This level is only available if implemented by the hypervisor.

hypervisor level 4000_0003h

input

EAX=4000_0003h

get hypervisor information – features ^#1

output

EAX

bits

description of features based on current privileges

31...13

reserved

12

debug MSRs

11

timer frequency MSRs

10

virtual guest idle state MSR

9

partition reference TSC MSR

8

access statistics pages MSRs

7

virtual system reset MSR

6

access virtual processor index MSR

5

hypercall MSRs

4

APIC access MSRs

3

synthetic timer MSRs

2

basic SyncIC MSRs

1

partition reference counter

0

VP runtime

EBX

bits

description of flags specified at creation time

31...14

reserved

13

ConfigureProfiler

12

CpuManagement

11

Debugging

10

reserved

9

reserved

8

AccessStats

7

ConnectPort

6

CreatePort

5

SignalEvents

4

PostMessages

3

AdjustMessageBuffers

2

AccessMemoryPool

1

AccessPartitionId

0

CreatePartition

ECX

bits

description of power management information

31...5

reserved

4

HPET is required to enter C3

3..0

maximum processor power state (0=C0, 1=C1, 2=C2, 3=C3)

EDX

bits

description of miscellaneous available features

31...12

reserved

11

debug MSRs

10

guest crash MSRs

9

inject synthetic MCs

8

determine timer frequencies

7

query NUMA distances

6

hypervisior sleep state

5

virtual guest idle state

4

hypercall input parameter block via XMM

3

physical CPU dynamic partitioning events

2

performance monitor

1

guest debugging

0

MWAIT

note

description

#1

This level is only available if implemented by the hypervisor.

hypervisor level 4000_0004h

input

EAX=4000_0004h

get hypervisor information – recommendations ^#1

output

EAX

bits

description

31...10

reserved

9

deprecate AutoEOI

8

x2APIC MSRs

7

interrupt remapping

6

DMA remapping

5

relaxed timing – disable watchdogs

4

MSR for system reset

3

MSRs for APIC EOI/ICR/TPR

2

hypercall for remote TLB flush

1

hypercall for local TLB flush

0

hypercall for address space switch

EBX

bits

description

31...0

recommended spinlock failure retries (FFFF_FFFFh = -1 = never)

ECX

bits

description

31...0

reserved

EDX

bits

description

31...0

reserved

note

description

#1

This level is only available if implemented by the hypervisor.

hypervisor level 4000_0005h

input

EAX=4000_0005h

get hypervisor information – limits ^#1

output

EAX

bits

description

31...0

maximum supported virtual processors

EBX

bits

description

31...0

maximum supported logical processors

ECX

bits

description

31...0

maximum supported physical interrupt vectors for remapping

EDX

bits

description

31...0

reserved

note

description

#1

This level is only available if implemented by the hypervisor.

hypervisor level 4000_0006h

input

EAX=4000_0006h

get hypervisor information – hardware features detected and in use^#1

output

EAX

bits

description

31...7

reserved

6

memory patrol scrubber

5

interrupt remapping

4

DMA remapping

3

second level address translation

2

architectural performance counters

1

MSR bitmaps

0

APIC overlay assist

EBX

bits

description

31...0

reserved

ECX

bits

description

31...0

reserved

EDX

bits

description

31...0

reserved for future AMD-specific features

note

description

#1

This level is only available if implemented by the hypervisor.

extended level 8000_0000h

input

EAX=8000_0000h

get maximum supported extended level and vendor ID string

output

EAX=xxxx_xxxxh

maximum supported extended level

EBX-EDX-ECX

vendor ID string

AuthenticAMD

AMD processor

reserved

Cyrix processor

reserved

Centaur processor

reserved

Intel processor

TransmetaCPU

Transmeta processor

reserved

National Semiconductor processor (GX1, GXLV, GXm)

Geode by NSC

National Semiconductor processor (GX2)

extended level 8000_0001h

input

EAX=8000_0001h

get processor family/model/stepping and features flags

output

EAX=xxxx_xxxxh

processor family/model/stepping

extended family
(add)

The extended processor family is encoded in bits 27...20.

00+F

AMD K8 (Fam 08h)
Transmeta Efficeon

01+F

AMD K8L (Fam 10h)

02+F

AMD K8 (Fam 11h)

03+F

AMD K8L (Fam 12h)

05+F

AMD BC (Fam 14h)

06+F

AMD BD (Fam 15h)

07+F

AMD JG (Fam 16h)

08+F

AMD ZN (Fam 17h)

extended model
(concat)

The extended processor model is encoded in bits 19...16.

AMD K8

0

130 nm Rev C

1

90 nm Rev D

2

90 nm Rev E

4

90 nm Rev F

5

90 nm Rev F

6

65 nm Rev G

7

65 nm Rev G

C

90 nm Rev F (in Fr3)

AMD Fam 15h

0

OR

1

TN/RL

3

KV/GV

6

CZ/BR

7

ST

AMD Fam 16h

0

KB/BV

3

ML

6

NL

AMD Fam 17h

0

ZP

1

RV

family

The family is encoded in bits 11...8.

5

AMD K5
Geode
Centaur C2 and C3
Transmeta Crusoe

6

AMD K6
VIA C3

7

AMD K7

F

refer to extended family

model

The model is encoded in bits 7...4.

AMD K5

1

5k86 (PR120 or PR133)

2

5k86 (PR166)

3

5k86 (PR200)

AMD K6

6

K6 (0.30 µm)

7

K6 (0.25 µm)

8

K6-2

9

K6-III

D

K6-2+ or K6-III+ (0.18 µm)

AMD K7

1

Athlon (0.25 µm)

2

Athlon (0.18 µm)

3

Duron (SF core)

4

Athlon (TB core)

6

Athlon (PM core)

7

Duron (MG core)

8

Athlon (TH/AP core)

A

Athlon (BT core)

AMD K8 (Fam 08h)

xx00b

Socket 754 or Socket S1

xx01b

Socket 940 or Socket F1207

xx10b

if Rev CG, then see K8 erratum #108

xx11b

Socket 939 or Socket AM2 or ASB1

01xxb

SH (SC 1024 KB)

11xxb

DH (SC 512 KB)

10xxb

CH (SC 256 KB)

00xxb

JH (DC 1024 KB)

10xxb

BH (DC 512 KB)

AMD K8L (Fam 10h)

0

Rev A DR (0/1/2=A0/A1/A2)

2

Rev B DR (0/1/A/2/3=B0/B1/BA/B2/B3)

4/5/6

Rev C RB/BL/DA (0/1/2/3=C0/C1/C2/C3)

8/9

Rev D HY SCM/MCM (0/1=D0/D1)

A

Rev E PH (0=E0)

AMD K8 (Fam 11h)

3

Rev B LG (1=B1)

AMD K8L (Fam 12h)

0

Rev A LN1 (0/1=A0/A1)

1

Rev B LN1 (0=B0)

2

Rev B LN2 (0=B0)

AMD BC (Fam 14h)

1

Rev B ON (0=B0)

2

Rev C ON (0=C0)

AMD BD (Fam 15h)

00

Rev A OR (0/1=A0/A1)

01

Rev B OR (0/1/2=B0/B1/B2)

02

Rev C OR (0=C0)

10

Rev A TN (1=A1)

13

Rev A RL (1=A1)

30

Rev A KV (0/1=A0/A1)

38

Rev A GV (1=A1)

60

Rev A CZ (0/1=A0/A1)

65

OSVW.ID5=0: Rev A CZ DDR4 (1=A1)
OSVW.ID5=1: Rev A BR (1=A1)

70

Rev A ST (0=A0)

AMD JG (Fam 16h)

00

Rev A KB (0/1=A0/A1)

04

Rev A BV (1=A1)

30

Rev A ML (0/1=A0/A1)

60

Rev A NL (1=A1)

AMD ZN (Fam 17h)

00

Rev A ZP (1=A1)

10

Rev A RV (1=A1)

Geode

4

GX1, GXLV, GXm

5

GX2

5

LX

Centaur

8

C2

9

C3

VIA C3

5

Cyrix M2 core

6

WinChip C5A core

7

WinChip C5B core (if stepping = 0...7)

7

WinChip C5C core (if stepping = 8...F)

8

WinChip C5N core (if stepping = 0...7)

9

WinChip C5XL core (if stepping = 0...7)

9

WinChip C5P core (if stepping = 8...F)

10

WinChip C5J core

Transmeta Crusoe

4

TM3x00 and TM5x00

Transmeta Efficeon

2

TM8000 (130 nm)

2

TM8000 (90 nm CMS 6.0)

3

TM8000 (90 nm CMS 6.1+)

stepping

The stepping is encoded in bits 3...0.

The stepping values are processor-specific.

EBX=x000_xxxxh

package type

The package type is encoded in bits 31...28.

AMD K8L (Fam 10h)

0000b

Socket F

0001b

Socket AM

0010b

Socket S1

0011b

Socket G34

0100b

Socket ASB2

0101b

Socket C32

other

reserved

AMD K8L (Fam 12h)

0001b

Socket FS1 (µPGA)

0010b

Socket FM1 (PGA)

AMD BC (Fam 14h)

0000b

Socket FT1 (BGA)

AMD BD (Fam 15h)
extended model 0

0001b

Socket AM3

0011b

Socket G34

0101b

Socket C32

AMD BD (Fam 15h)
extended model 1

0000b

Socket FP2 (BGA)

0001b

Socket FS1r2 (µPGA)

0010b

Socket FM2 (PGA)

AMD BD (Fam 15h)
extended model 3

0000b

Socket FP3 (BGA)

0001b

Socket FM2r2 (µPGA)

AMD BD (Fam 15h)
extended model 6

0000b

Socket FP4 (BGA)

0010b

Socket AM4 (µPGA)

0011b

Socket FM2r2 (µPGA)

AMD BD (Fam 15h)
extended model 7

0000b

Socket FP4 (BGA)

0010b

Socket AM4 (µPGA)

0100b

Socket FT4 (BGA)

AMD JG (Fam 16h) extended model 0

0000b

Socket FT3 (BGA)

0001b

Socket FS1b

AMD JG (Fam 16h) extended model 3

0000b

Socket FT3b (BGA)

0011b

Socket FP4

AMD ZP (Fam 17h) extended model 0

0001b

Socket SP4

0010b

Socket AM4

0011b

Socket SP4r2

0100b

Socket SP3

0111b

Socket SP3r2

AMD RV (Fam 17h) extended model 1

0000b

Socket FP5

0010b

Socket AM4

brand ID

The brand ID is encoded in bits 15...0.

AMD K8 DDR1

ID = bits 15...6 = (value >> 6) & 3FFh
NN = bits 5...0 = value & 3Fh

for NN=1...63: XX = 22 + NN
for NN=1...30: YY = 38 + (2 * NN)
for NN=1...63: ZZ = 24 + NN
for NN=1...63: TT = 24 + NN
for NN=1...11: RR = 45 + (5 * NN)
for NN=1...31: EE = 9 + NN

00h

engineering sample

04h

AMD Athlon 64 XX00+

05h

AMD Athlon 64 X2 XX00+

06h

AMD Athlon 64 FX-ZZ

08h

AMD Athlon 64 XX00+ mobile

09h

AMD Athlon 64 XX00+ mobile, low power

0Ah

AMD Turion 64 ML-XX

0Bh

AMD Turion 64 MT-XX

0Ch

AMD Opteron 1YY

0Dh

AMD Opteron 1YY

0Eh

AMD Opteron 1YY HE

0Fh

AMD Opteron 1YY EE

10h

AMD Opteron 2YY

11h

AMD Opteron 2YY

12h

AMD Opteron 2YY HE

13h

AMD Opteron 2YY EE

14h

AMD Opteron 8YY

15h

AMD Opteron 8YY

16h

AMD Opteron 8YY HE

17h

AMD Opteron 8YY EE

18h

AMD Athlon 64 EE00+

1Dh

AMD Athlon XP-M XX00+ mobile, 32-bit

1Eh

AMD Athlon XP-M XX00+ mobile, 32-bit, low power

20h

AMD Athlon XP XX00+, 32-bit

21h

AMD Sempron TT00+ mobile, 32-bit

23h

AMD Sempron TT00+ mobile, 32-bit, low power

22h

AMD Sempron TT00+, 32-bit

26h

AMD Sempron TT00+, 64-bit

24h

AMD Athlon 64 FX-ZZ

29h

AMD Opteron DC 1RR SE

2Ah

AMD Opteron DC 2RR SE

2Bh

AMD Opteron DC 8RR SE

2Ch

AMD Opteron DC 1RR

2Dh

AMD Opteron DC 1RR

2Eh

AMD Opteron DC 1RR HE

2Fh

AMD Opteron DC 1RR EE

30h

AMD Opteron DC 2RR

31h

AMD Opteron DC 2RR

32h

AMD Opteron DC 2RR HE

33h

AMD Opteron DC 2RR EE

34h

AMD Opteron DC 8RR

35h

AMD Opteron DC 8RR

36h

AMD Opteron DC 8RR HE

37h

AMD Opteron DC 8RR EE

38h

AMD Opteron DC 1RR

39h

AMD Opteron DC 2RR

3Ah

AMD Opteron DC 8RR

3Bh

AMD Opteron DC 1RR

3Ch

AMD Opteron DC 2RR

3Dh

AMD Opteron DC 8RR

other

unknown

AMD K8 DDR2

S = socket (see CPUID model bits 1...0)
CC = core count - 1 (see NB capabilities register)
ID = bits 13...9
PL = bits 8...6 and 14
NN = bits 15 and 5...0

RR = -1 + NN^*
PP = 26 + NN
TT = 15 + (CC * 10) + NN
ZZ = 57 + NN^**
YY = 29 + NN

000001b...000010b/100010b...111111b = 1...2/34...63 are reserved
** 100010b...111111b = 34...63 are reserved

S=any CC=? ID=00h PL=0h

engineering sample

S=AM2 CC=0 ID=01h PL=5h

AMD Sempron LE-1RR0

S=AM2 CC=0 ID=02h PL=6h

AMD Athlon LE-1ZZ0

S=AM2 CC=0 ID=03h PL=6h

AMD Athlon 1ZZ0B

S=AM2 CC=0 ID=04h PL=1h

AMD Athlon 64 TT00+

S=AM2 CC=0 ID=04h PL=2h

AMD Athlon 64 TT00+

S=AM2 CC=0 ID=04h PL=3h

AMD Athlon 64 TT00+

S=AM2 CC=0 ID=04h PL=4h

AMD Athlon 64 TT00+

S=AM2 CC=0 ID=04h PL=5h

AMD Athlon 64 TT00+

S=AM2 CC=0 ID=04h PL=8h

AMD Athlon 64 TT00+

S=AM2 CC=0 ID=05h PL=2h

AMD Sempron RR50p

S=AM2 CC=0 ID=06h PL=4h

AMD Sempron TT00+

S=AM2 CC=0 ID=06h PL=8h

AMD Sempron TT00+

S=ASB1 CC=0 ID=07h PL=1h

AMD Sempron TT0U

S=ASB1 CC=0 ID=07h PL=2h

AMD Sempron TT0U

S=AM2 CC=0 ID=08h PL=2h

AMD Athlon TT50e

S=AM2 CC=0 ID=08h PL=3h

AMD Athlon TT50e

S=ASB1 CC=0 ID=09h PL=2h

AMD Athlon Neo MV-TT

S=ASB1 CC=0 ID=0Ch PL=2h

AMD Sempron 2RRU

S=AM2 CC=1 ID=01h PL=6h

AMD Opteron DC 12RR HE

S=AM2 CC=1 ID=01h PL=Ah

AMD Opteron DC 12RR

S=AM2 CC=1 ID=01h PL=Ch

AMD Opteron DC 12RR SE

S=AM2 CC=1 ID=03h PL=3h

AMD Athlon X2 BE-2TT0

S=AM2 CC=1 ID=04h PL=1h

AMD Athlon 64 X2 TT00+

S=AM2 CC=1 ID=04h PL=2h

AMD Athlon 64 X2 TT00+

S=AM2 CC=1 ID=04h PL=6h

AMD Athlon 64 X2 TT00+

S=AM2 CC=1 ID=04h PL=8h

AMD Athlon 64 X2 TT00+

S=AM2 CC=1 ID=04h PL=Ch

AMD Athlon 64 X2 TT00+

S=AM2 CC=1 ID=05h PL=Ch

AMD Athlon 64 FX-ZZ

S=AM2 CC=1 ID=06h PL=6h

AMD Sempron RR00

S=AM2 CC=1 ID=07h PL=3h

AMD Athlon TT50e

S=AM2 CC=1 ID=07h PL=6h

AMD Athlon TT00B

S=AM2 CC=1 ID=07h PL=7h

AMD Athlon TT00B

S=AM2 CC=1 ID=08h PL=3h

AMD Athlon TT50B

S=AM2 CC=1 ID=09h PL=1h

AMD Athlon X2 TT50e

S=AM2 CC=1 ID=0Ah PL=1h

AMD Athlon Neo X2 TT50e

S=AM2 CC=1 ID=0Ah PL=2h

AMD Athlon Neo X2 TT50e

S=ASB1 CC=1 ID=0Bh PL=0h

AMD Turion Neo X2 L6RR

S=ASB1 CC=1 ID=0Ch PL=0h

AMD Athlon Neo X2 L3RR

S=S1 CC=0 ID=01h PL=2h

AMD Athlon 64 TT00+

S=S1 CC=0 ID=02h PL=Ch

AMD Turion 64 MK-YY

S=S1 CC=0 ID=03h PL=1h

AMD Sempron TT00+ mobile

S=S1 CC=0 ID=03h PL=6h

AMD Sempron PP00+ mobile

S=S1 CC=0 ID=03h PL=Ch

AMD Sempron PP00+ mobile

S=S1 CC=0 ID=04h PL=2h

AMD Sempron TT00+

S=S1 CC=0 ID=06h PL=4h

AMD Athlon TF-TT

S=S1 CC=0 ID=06h PL=6h

AMD Athlon TF-TT

S=S1 CC=0 ID=06h PL=Ch

AMD Athlon TF-TT

S=S1 CC=0 ID=07h PL=3h

AMD Athlon L1RR

S=S1 CC=1 ID=01h PL=Ch

AMD Sempron TJ-YY

S=S1 CC=1 ID=02h PL=Ch

AMD Turion 64 X2 TL-YY

S=S1 CC=1 ID=03h PL=4h

AMD Athlon 64 X2 TK-YY

S=S1 CC=1 ID=03h PL=Ch

AMD Athlon 64 X2 TK-YY

S=S1 CC=1 ID=05h PL=4h

AMD Athlon 64 X2 TT00+

S=S1 CC=1 ID=06h PL=2h

AMD Athlon X2 L3RR

S=S1 CC=1 ID=07h PL=4h

AMD Turion X2 L5RR

S=F1207 CC=0 ID=01h PL=2h

AMD Opteron 22RR EE

S=F1207 CC=1 ID=00h PL=2h

AMD Opteron DC 12RR EE

S=F1207 CC=1 ID=00h PL=6h

AMD Opteron DC 12RR HE

S=F1207 CC=1 ID=01h PL=2h

AMD Opteron DC 22RR EE

S=F1207 CC=1 ID=01h PL=6h

AMD Opteron DC 22RR HE

S=F1207 CC=1 ID=01h PL=Ah

AMD Opteron DC 22RR

S=F1207 CC=1 ID=01h PL=Ch

AMD Opteron DC 22RR SE

S=F1207 CC=1 ID=04h PL=2h

AMD Opteron DC 82RR EE

S=F1207 CC=1 ID=04h PL=6h

AMD Opteron DC 82RR HE

S=F1207 CC=1 ID=04h PL=Ah

AMD Opteron DC 82RR

S=F1207 CC=1 ID=04h PL=Ch

AMD Opteron DC 82RR SE

S=F1207 CC=1 ID=06h PL=Eh

AMD Athlon 64 FX-ZZ (Fr3)

AMD K8L (Fam 10h)

PT = package type (se EBX bits 31...28)
NC = number of cores (see level 8000_0008h)

PG = bit 15
S1 = bits 14...11
M = bits 10...4
S2 = bits 3...0

PT=0 PG=0 NC=3 S1=0h

QC AMD Opteron Processor 83

PT=0 PG=0 NC=3 S1=1h

QC AMD Opteron Processor 23

PT=0 PG=0 NC=5 S1=0h

6C AMD Opteron Processor 84

PT=0 PG=0 NC=5 S1=1h

6C AMD Opteron Processor 24

PT=0 PG=1 NC=3 S1=1h

Embedded AMD Opteron Processor_

PT=0 PG=1 NC=5 S1=1h

Embedded AMD Opteron Processor_

PT=0 PG=0 NC=3 S2=Ah

SE

PT=0 PG=0 NC=3 S2=Bh

HE

PT=0 PG=0 NC=3 S2=Ch

EE

PT=0 PG=0 NC=5 S2=0h

SE

PT=0 PG=0 NC=5 S2=1h

HE

PT=0 PG=0 NC=5 S2=2h

EE

PT=0 PG=0 NC=x S2=Fh

(empty)

PT=0 PG=1 NC=3 S2=1h

GF HE

PT=0 PG=1 NC=3 S2=2h

HF HE

PT=0 PG=1 NC=3 S2=3h

VS

PT=0 PG=1 NC=3 S2=4h

QS HE

PT=0 PG=1 NC=3 S2=5h

NP HE

PT=0 PG=1 NC=3 S2=6h

KH HE

PT=0 PG=1 NC=3 S2=7h

KS EE

PT=0 PG=1 NC=5 S2=1h

QS

PT=0 PG=1 NC=5 S2=2h

KS HE

PT=1 PG=0 NC=0 S1=2h

AMD Sempron 1

PT=1 PG=0 NC=0 S1=3h

AMD Athlon II 1

PT=1 PG=0 NC=1 S1=1h

AMD Athlon_

PT=1 PG=0 NC=1 S1=3h

AMD Athlon II X2 2

PT=1 PG=0 NC=1 S1=4h

AMD Athlon II X2 B

PT=1 PG=0 NC=1 S1=5h

AMD Athlon II X2_

PT=1 PG=0 NC=1 S1=7h

AMD Phenom II X2 5

PT=1 PG=0 NC=1 S1=Ah

AMD Phenom II X2_

PT=1 PG=0 NC=1 S1=Bh

AMD Phenom II X2 B

PT=1 PG=0 NC=1 S1=Ch

AMD Sempron X2 1

PT=1 PG=0 NC=2 S1=0h

AMD Phenom_

PT=1 PG=0 NC=2 S1=3h

AMD Phenom II X3 B

PT=1 PG=0 NC=2 S1=4h

AMD Phenom II X3_

PT=1 PG=0 NC=2 S1=7h

AMD Athlon II X3 4

PT=1 PG=0 NC=2 S1=8h

AMD Phenom II X3 7

PT=1 PG=0 NC=2 S1=Ah

AMD Athlon II X3_

PT=1 PG=0 NC=3 S1=0h

QC AMD Opteron Processor 13

PT=1 PG=0 NC=3 S1=2h

AMD Phenom_

PT=1 PG=0 NC=3 S1=3h

AMD Phenom II X4 9

PT=1 PG=0 NC=3 S1=4h

AMD Phenom II X4 8

PT=1 PG=0 NC=3 S1=7h

AMD Phenom II X4 B

PT=1 PG=0 NC=3 S1=8h

AMD Phenom II X4_

PT=1 PG=0 NC=3 S1=Ah

AMD Athlon II X4 6

PT=1 PG=0 NC=3 S1=Fh

AMD Athlon II X4_

PT=1 PG=0 NC=5 S1=0h

AMD Phenom II X6 1

PT=1 PG=1 NC=1 S1=1h

AMD Athlon II XLT V

PT=1 PG=1 NC=1 S1=2h

AMD Athlon II XL V

PT=1 PG=1 NC=3 S1=1h

AMD Phenom II XLT Q

PT=1 PG=1 NC=3 S1=2h

AMD Phenom II X4 9

PT=1 PG=1 NC=3 S1=3h

AMD Phenom II X4 8

PT=1 PG=1 NC=3 S1=4h

AMD Phenom II X4 6

PT=1 PG=0 NC=0 S2=Ah

Processor

PT=1 PG=0 NC=0 S2=Bh

u Processor

PT=1 PG=0 NC=1 S2=3h

50 DC Processor

PT=1 PG=0 NC=1 S2=6h

Processor

PT=1 PG=0 NC=1 S2=7h

e Processor

PT=1 PG=0 NC=1 S2=9h

0 Processor

PT=1 PG=0 NC=1 S2=Ah

0e Processor

PT=1 PG=0 NC=1 S2=Bh

u Processor

PT=1 PG=0 NC=2 S2=0h

00 3C Processor

PT=1 PG=0 NC=2 S2=1h

00e 3C Processor

PT=1 PG=0 NC=2 S2=2h

00B 3C Processor

PT=1 PG=0 NC=2 S2=3h

50 3C Processor

PT=1 PG=0 NC=2 S2=4h

50e 3C Processor

PT=1 PG=0 NC=2 S2=5h

50B 3C Processor

PT=1 PG=0 NC=2 S2=6h

Processor

PT=1 PG=0 NC=2 S2=7h

e Processor

PT=1 PG=0 NC=2 S2=9h

0e Processor

PT=1 PG=0 NC=2 S2=Ah

0 Processor

PT=1 PG=0 NC=3 S2=0h

00 QC Processor

PT=1 PG=0 NC=3 S2=1h

00e QC Processor

PT=1 PG=0 NC=3 S2=2h

00B QC Processor

PT=1 PG=0 NC=3 S2=3h

50 QC Processor

PT=1 PG=0 NC=3 S2=4h

50e QC Processor

PT=1 PG=0 NC=3 S2=5h

50B QC Processor

PT=1 PG=0 NC=3 S2=6h

Processor

PT=1 PG=0 NC=3 S2=7h

e Processor

PT=1 PG=0 NC=3 S2=9h

0e Processor

PT=1 PG=0 NC=3 S2=Eh

0 Processor

PT=1 PG=0 NC=5 S2=0h

5T Processor

PT=1 PG=0 NC=5 S2=1h

0T Processor

PT=1 PG=0 NC=x S2=Fh

(empty)

PT=1 PG=1 NC=1 S2=1h

L Processor

PT=1 PG=1 NC=1 S2=2h

C Processor

PT=1 PG=1 NC=3 S2=1h

L Processor

PT=1 PG=1 NC=3 S2=4h

T Processor

PT=2 PG=0 NC=0 S1=0h

AMD Sempron M1

PT=2 PG=0 NC=0 S1=1h

AMD V

PT=2 PG=0 NC=1 S1=0h

AMD Turion II Ultra DC Mobile M6

PT=2 PG=0 NC=1 S1=1h

AMD Turion II DC Mobile M5

PT=2 PG=0 NC=1 S1=2h

AMD Athlon II DC M3

PT=2 PG=0 NC=1 S1=3h

AMD Turion II P

PT=2 PG=0 NC=1 S1=4h

AMD Athlon II P

PT=2 PG=0 NC=1 S1=5h

AMD Phenom II X

PT=2 PG=0 NC=1 S1=6h

AMD Phenom II N

PT=2 PG=0 NC=1 S1=7h

AMD Turion II N

PT=2 PG=0 NC=1 S1=8h

AMD Athlon II N

PT=2 PG=0 NC=1 S1=9h

AMD Phenom II P

PT=2 PG=0 NC=2 S1=2h

AMD Phenom II P

PT=2 PG=0 NC=2 S1=3h

AMD Phenom II N

PT=2 PG=0 NC=2 S1=4h

AMD Phenom II X

PT=2 PG=0 NC=3 S1=1h

AMD Phenom II P

PT=2 PG=0 NC=3 S1=2h

AMD Phenom II X

PT=2 PG=0 NC=3 S1=3h

AMD Phenom II N

PT=2 PG=0 NC=0 S2=1h

0 Processor

PT=2 PG=0 NC=1 S2=2h

0 DC Processor

PT=2 PG=0 NC=2 S2=2h

0 3C Processor

PT=2 PG=0 NC=3 S2=1h

0 QC Processor

PT=2 PG=0 NC=x S2=Fh

(empty)

PT=3 PG=0 NC=7 S1=0h

AMD Opteron Processor 61

PT=3 PG=0 NC=B S1=0h

AMD Opteron Processor 61

PT=3 PG=1 NC=7 S1=1h

Embedded AMD Opteron Processor_

PT=3 PG=0 NC=7 S2=0h

HE

PT=3 PG=0 NC=7 S2=1h

SE

PT=3 PG=0 NC=B S2=0h

HE

PT=3 PG=0 NC=B S2=1h

SE

PT=3 PG=0 NC=x S2=Fh

(empty)

PT=3 PG=1 NC=7 S2=1h

QS

PT=3 PG=1 NC=7 S2=2h

KS

PT=4 PG=0 NC=0 S1=1b

AMD Athlon II Neo K

PT=4 PG=0 NC=0 S1=2b

AMD V

PT=4 PG=0 NC=0 S1=3b

AMD Athlon II Neo R

PT=4 PG=0 NC=1 S1=1b

AMD Turion II Neo K

PT=4 PG=0 NC=1 S1=2b

AMD Athlon II Neo K

PT=4 PG=0 NC=1 S1=3b

AMD V

PT=4 PG=0 NC=1 S1=4b

AMD Turion II Neo N

PT=4 PG=0 NC=1 S1=5b

AMD Athlon II Neo N

PT=4 PG=0 NC=0 S2=1h

5 Processor

PT=4 PG=0 NC=0 S2=2h

L Processor

PT=4 PG=0 NC=1 S2=1h

5 DC Processor

PT=4 PG=0 NC=1 S2=2h

L DC Processor

PT=4 PG=0 NC=1 S2=4h

H DC Processor

PT=4 PG=0 NC=x S2=Fh

(empty)

PT=5 PG=0 NC=3 S1=0h

AMD Opteron Processor 41

PT=5 PG=0 NC=5 S1=0h

AMD Opteron Processor 41

PT=5 PG=1 NC=3 S1=1h

Embedded AMD Opteron Processor_

PT=5 PG=1 NC=5 S1=1h

Embedded AMD Opteron Processor_

PT=5 PG=0 NC=3 S2=0h

HE

PT=5 PG=0 NC=3 S2=1h

EE

PT=5 PG=0 NC=5 S2=0h

HE

PT=5 PG=0 NC=5 S2=1h

EE

PT=5 PG=0 NC=x S2=Fh

(empty)

PT=5 PG=1 NC=3 S2=1h

QS HE

PT=5 PG=1 NC=3 S2=2h

LE HE

PT=5 PG=1 NC=3 S2=3h

CL EE

PT=5 PG=1 NC=5 S2=1h

KX HE

PT=5 PG=1 NC=5 S2=2h

GL EE

AMD K8L (Fam 11h)

PT = package type (se EBX bits 31...28)
NC = number of cores (see level 8000_0008h)

PG = bit 15
S1 = bits 14...11
M = bits 10...4
S2 = bits 3...0

PT=2 PG=0 NC=0 S1=0h

AMD Sempron SI-

PT=2 PG=0 NC=0 S1=1h

AMD Athlon QI-

PT=2 PG=0 NC=1 S1=0h

AMD Turion X2 Ultra Dual-Core Mobile ZM-

PT=2 PG=0 NC=1 S1=1h

AMD Turion X2 Dual-Core Mobile RM-

PT=2 PG=0 NC=1 S1=2h

AMD Athlon X2 Dual-Core QL-

PT=2 PG=0 NC=1 S1=3h

AMD Sempron X2 Dual-Core NI-

PT=2 PG=0 NC=0 S2=0h

(empty)

PT=2 PG=0 NC=1 S2=0h

(empty)

PT=2 PG=0 NC=x S2=Fh

(empty)

AMD K8L (Fam 12h)

PT = package type (se EBX bits 31...28)
NC = number of cores (see level 8000_0008h)

PG = bit 15
S1 = bits 14...11
M = bits 10...4
S2 = bits 3...0

PT=1 PG=0 NC=1 S1=3h

AMD A4-33

PT=1 PG=0 NC=1 S1=5h

AMD E2-30

PT=1 PG=0 NC=4 S1=1h

AMD A8-35

PT=1 PG=0 NC=4 S1=3h

AMD A6-34

PT=1 PG=0 NC=1 S2=1h

M APU with Radeon HD Graphics

PT=1 PG=0 NC=1 S2=2h

MX APU with Radeon HD Graphics

PT=1 PG=0 NC=3 S2=1h

M APU with Radeon HD Graphics

PT=1 PG=0 NC=3 S2=2h

MX APU with Radeon HD Graphics

PT=1 PG=0 NC=x S2=Fh

(empty)

PT=2 PG=0 NC=1 S1=1h

AMD A4-33

PT=2 PG=0 NC=1 S1=2h

AMD E2-32

PT=2 PG=0 NC=1 S1=4h

AMD Athlon II X2 2

PT=2 PG=0 NC=1 S1=5h

AMD A4-34

PT=2 PG=0 NC=1 S1=Ch

AMD Sempron X2 1

PT=2 PG=0 NC=2 S1=5h

AMD A6-35

PT=2 PG=0 NC=3 S1=5h

AMD A8-38

PT=2 PG=0 NC=3 S1=6h

AMD A6-36

PT=2 PG=0 NC=3 S1=Dh

AMD Athlon II X4 6

PT=2 PG=0 NC=1 S1=1h

APU with Radeon HD Graphics

PT=2 PG=0 NC=1 S1=2h

Dual-Core Processor

PT=2 PG=0 NC=2 S1=1h

APU with Radeon HD Graphics

PT=2 PG=0 NC=3 S1=1h

APU with Radeon HD Graphics

PT=2 PG=0 NC=3 S1=3h

Quad-Core Processor

PT=2 PG=0 NC=x S1=Fh

(empty)

AMD BC (Fam 14h)

PT = package type (se EBX bits 31...28)
NC = number of cores (see level 8000_0008h)

PG = bit 15
S1 = bits 14...11
M = bits 10...4
S2 = bits 3...0

PT=0 PG=0 NC=0 S1=1h

AMD C- (client)

PT=0 PG=0 NC=0 S1=2h

AMD E- (client)

PT=0 PG=0 NC=0 S1=4h

AMD G-T- (embedded)

PT=0 PG=0 NC=1 S1=1h

AMD C- (client)

PT=0 PG=0 NC=1 S1=2h

AMD E- (client)

PT=0 PG=0 NC=1 S1=3h

AMD Z- (tablet)

PT=0 PG=0 NC=1 S1=4h

AMD G-T- (embedded)

PT=0 PG=0 NC=1 S1=5h

AMD E1-1- (client)

PT=0 PG=0 NC=1 S1=6h

AMD E2-1- (client)

PT=0 PG=0 NC=1 S1=7h

AMD E2-2- (client)

PT=0 PG=0 NC=0 S2=1h

Processor

PT=0 PG=0 NC=0 S2=2h

0 Processor

PT=0 PG=0 NC=0 S2=3h

5 Processor

PT=0 PG=0 NC=0 S2=4h

0x Processor

PT=0 PG=0 NC=0 S2=5h

5x Processor

PT=0 PG=0 NC=0 S2=6h

x Processor

PT=0 PG=0 NC=0 S2=7h

L Processor

PT=0 PG=0 NC=0 S2=8h

N Processor

PT=0 PG=0 NC=0 S2=9h

R Processor

PT=0 PG=0 NC=0 S2=Ah

0 APU with Radeon HD Graphics

PT=0 PG=0 NC=0 S2=Bh

5 APU with Radeon HD Graphics

PT=0 PG=0 NC=0 S2=Ch

APU with Radeon HD Graphics

PT=0 PG=0 NC=0 S2=Dh

0D APU with Radeon HD Graphics

PT=0 PG=0 NC=1 S2=1h

Processor

PT=0 PG=0 NC=1 S2=2h

0 Processor

PT=0 PG=0 NC=1 S2=3h

5 Processor

PT=0 PG=0 NC=1 S2=4h

0x Processor

PT=0 PG=0 NC=1 S2=5h

5x Processor

PT=0 PG=0 NC=1 S2=6h

x Processor

PT=0 PG=0 NC=1 S2=7h

L Processor

PT=0 PG=0 NC=1 S2=8h

N Processor

PT=0 PG=0 NC=1 S2=9h

0 APU with Radeon HD Graphics

PT=0 PG=0 NC=1 S2=Ah

5 APU with Radeon HD Graphics

PT=0 PG=0 NC=1 S2=Bh

APU with Radeon HD Graphics

PT=0 PG=0 NC=1 S2=Ch

E Processor

PT=0 PG=0 NC=1 S2=Dh

0D APU with Radeon HD Graphics

PT=0 PG=0 NC=x S2=Fh

(empty)

ECX=xxxx_xxxxh

feature flags

description of indicated feature

bits 31

reserved

bits 30

reserved

bits 29 (MONX)

MONITORX/MWAITX

bit 28 (PCX_L2I / L3)

L2I perf counter extensions (MSRs C001_023[0...7]h) (Fam 15h/16h)
L3 perf counter extensions (MSRs C001_023[0...B]h) (Fam 17h)

bit 27 (PERFTSC)

performance TSC (MSR C001_0280h)

bit 26 (DBX)

data breakpoint extensions (MSRs C001_1027h and C001_10[19...1B]h)

bit 25

reserved

bit 24 (PCX_NB)

NB perf counter extensions (MSRs C001_024[0...7]h)

bit 23 (PCX_CORE)

core perf counter extensions (MSRs C001_020[0...B]h)

bit 22 (TOPX)

topology extensions: extended levels 8000_001Dh and 8000_001Eh

bit 21 (TBM)

TBM

bit 20

reserved

bit 19 (NODEID)

node ID: MSR C001_100Ch

bit 18

reserved

bit 17 (TCE)

translation cache extension, EFER.TCE

bit 16 (FMA4)

FMA4

bit 15 (LWP)

LWP

bit 14

reserved

bit 13 (WDT)

watchdog timer

bit 12 (SKINIT)

SKINIT, STGI, DEV

bit 11 (XOP)

XOP (was also used going to be used for SSE5A)

bit 10 (IBS)

instruction based sampling

bit 9 (OSVW)

OS-visible workaround

bit 8 (3DNow!P)

PREFETCH and PREFETCHW (K8 Rev G and K8L+)

bit 7 (MSSE)

misaligned SSE, MXCSR.MM

bit 6 (SSE4A)

SSE4A

bit 5 (LZCNT)

LZCNT

bit 4 (CR8D)

MOV from/to CR8D by means of LOCK-prefixed MOV from/to CR0

bit 3 (EAS)

extended APIC space (APIC_VER.EAS, EXT_APIC_FEAT, etc.)

bit 2 (SVM)

EFER.SVME
VMRUN, VMMCALL, VMLOAD and VMSAVE, STGI and CLGI,
SKINIT, INVLPGA bit 1 (CMP) HTT=1 indicates HTT (0) or CMP (1) bit 0 (AHF64) LAHF and SAHF in PM64

EDX=xxxx_xxxxh

feature flags

description of indicated feature

bit 31 (3DNow!)

3DNow!

bit 30 (3DNow!+)

extended 3DNow!

bit 29 (LM)

AMD64/EM64T, Long Mode

bit 28

reserved

bit 27 (TSCP)

TSC, TSC_AUX, RDTSCP, CR4.TSD

bit 26 (PG1G)

PML3E.PS

bit 25 (FFXSR)

EFER.FFXSR

bit 24 (MMX+)
bit 24 (FXSR)

Cyrix specific: extended MMX
AMD K7: FXSAVE/FXRSTOR, CR4.OSFXSR

bit 23 (MMX)

MMX

bit 22 (MMX+)

AMD specific: MMX-SSE and SSE-MEM

bit 21

reserved

bit 20 (NX)

EFER.NXE, P?E.NX, #PF(1xxxx)

bit 19 (MP)

MP-capable ^#3

bit 18

reserved

bit 17 (PSE36)

4 MB PDE bits 16...13, CR4.PSE

bit 16 (FCMOV)
bit 16 (PAT)

FCMOVcc/F(U)COMI(P) (implies FPU=1)
AMD K7: PAT MSR, PDE/PTE.PAT

bit 15 (CMOV)

CMOVcc

bit 14 (MCA)

MCG_*/MCn_* MSRs, CR4.MCE, #MC

bit 13 (PGE)

PDE/PTE.G, CR4.PGE

bit 12 (MTRR)

MTRR* MSRs

bit 11 (SEP)

SYSCALL/SYSRET, EFER/STAR MSRs ^#1

bit 10

reserved ^#1

bit 9 (APIC)

APIC ^#2

bit 8 (CX8)

CMPXCHG8B

bit 7 (MCE)

MCAR/MCTR MSRs, CR4.MCE, #MC

bit 6 (PAE)

64-bit PDPTE/PDE/PTEs, CR4.PAE

bit 5 (MSR)

MSRs, RDMSR/WRMSR

bit 4 (TSC)

TSC, RDTSC, CR4.TSD (doesn't imply MSR=1)

bit 3 (PSE)

PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb)

bit 2 (DE)

CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5

bit 1 (VME)

CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB

bit 0 (FPU)

FPU

notes

descriptions

#1

The AMD K6 processor, model 6, uses bit 10 to indicate SEP. Beginning with model 7, bit 11 is used instead.

Intel processors only report SEP when CPUID is executed in PM64.

#2

If the APIC has been disabled, then the APIC feature flag will read as 0.

#3

AMD K7 processors prior to CPUID=0662h may report 0 even if they are MP-capable.

extended levels 8000_0002h, 8000_0003h, and 8000_0004h

input

EAX=8000_0002h

get processor name string (part 1)

EAX=8000_0003h

get processor name string (part 2)

EAX=8000_0004h

get processor name string (part 3)

output

EAX
EBX
ECX
EDX

processor name string ^#1

AMD K5

AMD-K5(tm) Processor

AMD K6

AMD-K6tm w/ multimedia extensions

AMD K6-2

AMD-K6(tm) 3D processor
AMD-K6(tm)-2 Processor

AMD K6-III

AMD-K6(tm) 3D+ Processor
AMD-K6(tm)-III Processor

AMD K6-2+

AMD-K6(tm)-III Processor (?)

AMD K6-III+

AMD-K6(tm)-III Processor (?)

AMD K7

AMD-K7(tm) Processor (model 1)
AMD Athlon(tm) Processor (model 2)
newer models: programmable

AMD K8

programmable via MSRs C001_0030h...C001_0035h, default is 48x 0

AMD K8L

programmable via MSRs C001_0030h...C001_0035h, default is 48x 0

AMD BC

programmable via MSRs C001_0030h...C001_0035h, default is 48x 0

Geode GX2

Geode(TM) Integrated Processor by National Semi
programmable via MSRs 0000_300Ah...0000_300Fh

Geode LX

Geode(TM) Integrated Processor by AMD PCS
programmable via MSRs 0000_300Ah...0000_300Fh

Centaur C2 ^#2

IDT WinChip 2
IDT WinChip 2-3D

Centaur C3

IDT WinChip 3

VIA C3

CYRIX III(tm) (?)
VIA Samuel (?)
VIA Ezra (?)
VIA C3 Nehemiah (?)

Intel PM ^#3

Intel(R) Pentium(R) M processor xxxxMHz

Intel P4 ^#3

Intel(R) Pentium(R) 4 CPU xxxxMHz

Intel Core 2

Intel(R) Xeon(R) CPU xxxx @ x.xxGHz

Transmeta Crusoe

Transmeta(tm) Crusoe(tm) Processor TMxxxx

Transmeta Efficeon

Transmeta Efficeon(tm) Processor TM8000

notes

descriptions

#1

Unused characters at the end of the string are filled with 00h.

#2

The string depends on whether 3DNow! is disabled or enabled.

#3

The string is right-justified, with leading whitespaces.

extended level 8000_0005h

input

EAX=8000_0005h

get L1 cache and L1 TLB configuration descriptors ^#1

output

EAX

4/2 MB L1 TLB configuration descriptor

bits

description

31...24

data TLB associativity (FFh=full)

23...16

data TLB entries

15...8

code TLB associativity (FFh=full)

7...0

code TLB entries

EBX

4 KB L1 TLB configuration descriptor ^#2

bits

description

31...24

data TLB associativity (FFh=full)

23...16

data TLB entries

15...8

code TLB associativity (FFh=full)

7...0

code TLB entries

ECX

data L1 cache configuration descriptor

bits

description

31...24

data L1 cache size in KBs

23...16

data L1 cache associativity (FFh=full)

15...8

data L1 cache lines per tag

7...0

data L1 cache line size in bytes

EDX

code L1 cache configuration descriptor

bits

description

31...24

code L1 cache size in KBs

23...16

code L1 cache associativity (FFh=full)

15...8

code L1 cache lines per tag

7...0

code L1 cache line size in bytes

notes

descriptions

#1

Cyrix processors return CPUID level 0000_0002h-like descriptors instead. (Though the NS Geode GX2 does not.)

#2

While Transmeta Crusoe processors have 256 entries, the CPUID definition constrains them to reporting only 255.
For compatibility reasons they report their unified TLB twice: once for the code TLB, and once for the data TLB.

extended level 8000_0006h

input

EAX=8000_0006h

get L2/L3 cache and L2 TLB configuration descriptors

output

EAX

4/2 MB L2 TLB configuration descriptor ^#1

bits

description

31...28

data TLB associativity ^#2

27...16

data TLB entries

15...12

code TLB associativity ^#2

11...0

code TLB entries

EBX

4 KB L2 TLB configuration descriptor ^#1

bits

description

31...28

data TLB associativity ^#2

27...16

data TLB entries

15...12

code TLB associativity ^#2

11...0

code TLB entries

ECX

unified L2 cache configuration descriptor ^#3

bits

description

31...16 ^#5

unified L2 cache size in KBs ^#4

15...12 ^#5

unified L2 cache associativity ^{#2, #6}

11...8 ^#5

unified L2 cache lines per tag

7...0

unified L2 cache line size in bytes

EDX

unified L3 cache configuration descriptor

bits

description

31...18

unified L3 cache size in 512 KB chunks

17...16

reserved

15...12

unified L3 cache associativity ^#2

11...8

unified L3 cache lines per tag

7...0

unified L3 cache line size in bytes

notes

descriptions

#1

A unified L2 TLB is indicated by a value of 0000h in the upper 16 bits.

#2

0000b=disabled,
0001b=1-way, 0010b=2-way, 0011b=3-way, 0100b=4-way, 0101b=6-way, 0110b=8-way, 1000b=16-way,
1001b=see level 8000_001Dh instead,
1010b=32-way, 1011b=48-way, 1100b=64-way, 1101b=96-way, 1110b=128-way, 1111b=full

#3

The AMD K7 processor's L2 cache must be configured prior to relying upon this information, if the model is 1 or 2.

#4

AMD K7 processors with CPUID=0630h (Duron) inadvertently report 1 KB instead of 64 KB.

#5

VIA C3 processors with CPUID=0670...068Fh (C5B/C5C) inadvertently use bits 31...24, 23...16, and 15...8 instead.

#6

VIA C3 processors with CPUID=069x (C5XL) and stepping 1 inadvertently report 0 ways instead of 16 ways.

extended level 8000_0007h

input

EAX=8000_0007h

get capabilities

output

EAX

processor feedback capabilities

bits

description

31...16

maximum wrap time in ms

15...8

version (01h)

7...0

number of monitors (MSR C001_008[01]h etc.)

EBX

RAS capabilities

bits

description

31...5

reserved

4

reserved

3 (SCMCA)

scalable MCA (more banks, MCA ext regs, DOER/SEER roles)

2 (HWA)

hardware assert (MSR C001_10[DF...C0]h)

1 (SUCCOR)

software uncorrectable error containment and recovery

0 (MCAOVR)

MCA overflow recovery

ECX

advanced power monitoring interface

bits

description

31...0
(CmpUnitPwrSampleTimeRatio)

ratio of power accumulator sample period to GTSC counter period

EDX

enhanced power management capabilities

bits

description

31...15

reserved

14 (RAPL)

running average power limit

13 (CSB)

connected standby

12 (PA)

processor accumulator (MSR C001_007Ah)

11 (PFI)

processor feedback interface (see EAX)

10 (EFRO)

read-only MPERF/APERF (MSR C000_00E[78]h)

9 (CPB)

core performance boost

8 (ITSC)

invariant TSC

7 (HWPS)

hardware P-state support

6 (MUL100)

100 MHz multiplier steps

5 (STC)

software thermal control

4 (TM)

thermal monitoring

3 (TTP)

thermal trip

2 (VID)

voltage ID control

1 (FID)

frequency ID control

0 (TS)

temperature sensor

extended level 8000_0008h

input

EAX=8000_0008h

get miscellaneous information

output

EAX

address size information

bits

description

31...24

reserved

23...16

guest physical address bits (if 0, then see bits 7...0)

15...8

virtual address bits

7...0

physical address bits

EBX

feature flags

bits

description

31...19

reserved

18 (IBRS_PREF)

IBRS preferred

17 (STIBP_ALL)

STIBP always on mode

16 (IBRS_ALL)

IBRS always on mode

15 (STIBP)

SPEC_CTRL.STIBP

14 (IBRS)

SPEC_CTRL.IBRS

13

reserved

12 (IBPB)

PRED_CMD.IBPB

11...10

reserved

9 (WBNOINVD)

WBNOINVD

8 (MCOMMIT)

EFER.MCOMMIT, MCOMMIT

7...5

reserved

4 (RDPRU)

CR4.TSD, RDPRU

3

reserved

2 (ASRFPEP)

always save/restore FP error pointers

1 (IRPERF)

read-only IRPERF (MSR C000_00E9h)

0 (CLZERO)

CLZERO

ECX

processor count information

bits

description

31...18

reserved

17...16

performance TSC size (00b=40-bit, 01b=48-bit, 10b=56-bit, 11b=64-bit)

15...12

number of LSBs in APIC ID that indicate core ID

11...8

reserved

7...0

cores per die - 1

EDX

miscellaneous information

bits

description

31...16

maximum valid ECX value for RDPRU (0=MPERF, 1=APERF)

15...0

reserved

extended level 8000_000Ah

input

EAX=8000_000Ah

get SVM information

output

EAX

revision and presence information

bits

description

31...9

reserved

8

hypervisor present (and intercepting this bit, to advertise its presence)

7...0

revision, starting at 1

EBX

address space information

bits

description

31...0

number of ASIDs

EDX

sub-feature information

bits

description

31...17

reserved

16 (VGIF)

virtualized GIF

15 (VLS)

virtualized VMLOAD/VMSAVE

14

reserved

13 (AVIC)

AVIC

12 (PAUSEFILTERTHR.)

PAUSE filter threshold

11

reserved

10 (PAUSEFILTER)

PAUSE intercept filter

9 (SSSE3SSE5ADIS)

SSSE3 and SSE5A disable

8

reserved

7 (DECODEASSISTS)

decode assists

6 (FLUSHBYASID)

flush by ASID

5 (VMCBCLEAN)

VMCB clean bits

4 (TSCRATEMSR)

MSR-based TSC rate control

3 (NRIPS)

NRIP save on #VMEXIT

2 (SVML)

SVM lock

1 (LBRV)

LBR virtualization

0 (NP)

nested paging

extended level 8000_0019h

input

EAX=8000_0019h

get TLB configuration descriptors

output

EAX

1 GB L1 TLB configuration descriptor ^#1

bits

description

31...28

data TLB associativity ^#2

27...16

data TLB entries

15...12

code TLB associativity ^#2

11...0

code TLB entries

EBX

1 GB L2 TLB configuration descriptor ^#1

bits

description

31...28

data TLB associativity ^#2

27...16

data TLB entries

15...12

code TLB associativity ^#2

11...0

code TLB entries

notes

descriptions

#1

A unified TLB is indicated by a value of 0000h in the upper 16 bits.

#2

0000b=disabled, 0001b=1-way, 0010b=2-way, 0100b=4-way, 0110b=8-way, 1000b=16-way,
1010b=32-way, 1011b=48-way, 1100b=64-way, 1101b=96-way, 1110b=128-way, 1111b=full

extended level 8000_001Ah

input

EAX=8000_001Ah

get performance optimization identifiers

output

EAX

performance optimization identifiers

bits

description

31...3

reserved

2 (FP256)

1x 256-bit instead of 2x 128-bit processing

1 (MOVU)

prefer unaligned MOV over MOVL/MOVH

0 (FP128)

1x 128-bit instead of 2x 64-bit processing

extended level 8000_001Bh

input

EAX=8000_001Bh

get IBS information

output

EAX

IBS feature flags

bits

description

31...11

reserved

10

IBS op data 4 MSR

9

IBS fetch control extended MSR

8

fused branch micro-op indication

7

invalid RIP indication

6

IbsOpCurCnt and IbsOpMaxCnt extend by 7 bits

5

branch target address reporting

4

op counting mode

3

read write of op counter

2

IBS execution sampling

1

IBS fetch sampling

0

IBS feature flags valid

extended level 8000_001Ch

input

EAX=8000_001Ch

get LWP information

output

EAX

bits

description

31

interrupt on threshold overflow available

30

performance time stamp counter in event record available

29

sampling in continuous mode available

28...7

reserved

6

core reference clocks not halted event available

5

core clocks not halted event available

4

DC miss event available

3

branch retired event available

2

instructions retired event available

1

LWPVAL instruction available

0

LWP available (copy of XCR0.LWP)

EBX

bits

description

31...24

EventInterval1 field offset

23...16

maximum EventId

15...8

event record size

7...0

control block size

ECX

bits

description

31

cache latency filtering supported

30

cache level filtering supported

29

IP filtering supported

28

branch prediction filtering supported

27...24

reserved

23...16

event ring buffer size

15...9

version

8...6

amount by which cache latency is rounded

5

data cache miss address valid

4...0

latency counter bit size

EDX

bits

description

31

interrupt on threshold overflow supported

30

performance time stamp counter in event record supported

29

sampling in continuous mode supported

28...7

reserved

6

core reference clocks not halted event supported

5

core clocks not halted event supported

4

DC miss event supported

3

branch retired event supported

2

instructions retired event supported

1

LWPVAL instruction supported

0

LWP supported (copy of LWP feature flag in extended level 8000_0001h)

extended level 8000_001Dh

input

EAX=8000_001Dh

get cache configuration descriptors

ECX=xxxx_xxxxh

cache level to query (until EAX reports cache type = 0)

output

EAX

bits

description

31...26

reserved

25...14

cores per cache - 1

13...10

reserved

9

fully associative?

8

self-initializing?

7...5

cache level (starts at 1)

4...0

cache type (0=null, 1=data, 2=code, 3=unified, 4...31=reserved)

EBX

bits

description

31...22

ways of associativity - 1

21...12

physical line partitions - 1

11...0

system coherency line size - 1

ECX

bits

description

31...0

sets - 1

EDX

bits

description

31...2

reserved

1

inclusive of lower levels?

0

write-back invalidate?

extended level 8000_001Eh

input

EAX=8000_001Eh

get APIC/unit/node information

output

EAX

extended APIC ID

bits

description

31...0

extended APIC ID

EBX

compute unit identifiers (Fam 15h)
core identifiers (Fam 17h)

bits

description

31...16

reserved

15...8

cores per compute unit - 1 (Fam 15h)
threads per core - 1 (Fam 17h)

7...0

compute unit ID (Fam 15h)
core ID (Fam 17h)

ECX

node identifiers

bits

description

31...11

reserved

10...8

nodes per processor - 1

7...0

node ID

extended level 8000_001Fh

input

EAX=8000_001Fh

get SME/SEV information

output

EAX

bits

description

31...5

reserved

4

reserved

3

SEV-ES, VMGEXIT, #VC, GHCB MSR (C001_0130h)

2

VMPAGE_FLUSH MSR (C001_011Eh)

1

SEV

0

SME

EBX

bits

description

31...12

reserved

11...6

hPA bit count reduction when memory encryption is active

5...0

page table bit position used to indicate memory encryption

ECX

bits

description

31...0

number of simultaneously supported encrypted guests

EDX

bits

description

31...0

minimum SEV enabled, SEV-ES disabled ASID

Transmeta level 8086_0000h

input

EAX=8086_0000h

get maximum supported level and vendor ID string

output

EAX=xxxx_xxxxh

maximum supported level

EBX-EDX-ECX

vendor ID string

TransmetaCPU

Transmeta processor

Transmeta level 8086_0001h

input

EAX=8086_0001h

get processor information

output

EAX=xxxx_xxxxh

processor family/model/stepping

extended family
(add)

The extended processor family is encoded in bits 27...20.

00+0

Transmeta Efficeon

extended model
(concat)

The extended processor model is encoded in bits 19...16.

Transmeta Crusoe

0

TM3x00 and TM5x00

Transmeta Efficeon

0

TM8000

family

The family is encoded in bits 11...8.

5

Transmeta Crusoe

F

refer to extended family

model

The model is encoded in bits 7...4.

Transmeta Crusoe

4

TM3x00 and TM5x00

Transmeta Efficeon

2

TM8000 (130 nm)

2

TM8000 (90 nm CMS 6.0)

3

TM8000 (90 nm CMS 6.1+)

stepping

The stepping is encoded in bits 3...0.

The stepping values are processor-specific.

EBX=aabb_ccddh

hardware revision (a.b-c.d)
0101_xxyyh = TM3200
0102_xxyyh = TM5400
0103_xxyyh = TM5400 or TM5600
0103_00yyh = TM5500 or TM5800
0104_xxyyh = TM5500 or TM5800
0105_xxyyh = TM5500 or TM5800
0200_0000h = see level 8086_0002h register EAX

ECX=xxxx_xxxxh

nominal core clock frequency (MHz)

EDX=xxxx_xxxxh

feature flags

description of indicated feature

bits 31...4

reserved

bit 3 (LRTI)

LongRun Table Interface

bit 2 (???)

unknown

bit 1 (LR)

LongRun

bit 0 (BAD)

recovery CMS active (due to a failed upgrade)

Transmeta level 8086_0002h

input

EAX=8086_0002h

get processor information

output

EAX

xxxx_xxxxh

reserved or hardware revision (xxxxxxxxh)
see level 8086_0001h register EBX

EBX

aabb_ccddh

software revision, part 1/2 (a.b.c-d-x)

ECX

xxxx_xxxxh

software revision, part 2/2 (a.b.c-d-x)

Transmeta levels 8086_0003h, 8086_0004h, 8086_0005h, and 8086_0006h

input

EAX=8086_0003h

get information string (part 1)

EAX=8086_0004h

get information string (part 2)

EAX=8086_0005h

get information string (part 3)

EAX=8086_0006h

get information string (part 4)

output

EAX-EBX-ECX-EDX

information string ^#1

Transmeta

20000805 23:30 official release 4.1.4#2 (example)

note

description

#1

Unused characters at the end of the string are filled with 00h.

Transmeta level 8086_0007h

input

EAX=8086_0007h

get processor information

output

EAX

xxxx_xxxxh

current core clock frequency (MHz)

EBX

xxxx_xxxxh

current core clock voltage (mV)

ECX

xxxx_xxxxh

current (LongRun) performance level (0...100%)

EDX

xxxx_xxxxh

current gate delay (fs)

Centaur level C000_0000h

input

EAX=C000_0000h

get maximum supported level

output

EAX=xxxx_xxxxh

maximum supported level

Centaur level C000_0001h

input

EAX=C000_0001h

get processor information

output

EDX=xxxx_xxxxh

feature flags

description of indicated feature

bits 31...10

reserved

bit 9 (MM/HE-E)

Montgomery Multiplier and Hash Engine enabled

bit 8 (MM/HE)

Montgomery Multiplier and Hash Engine

bit 7 (ACE-E)

Advanced Cryptography Engine enabled

bit 6 (ACE)

Advanced Cryptography Engine

bit 5 (FEMMS)

FEMMS

bit 4 (LH)

LongHaul MSR 0000_110Ah

bit 3 (RNG-E)

Random Number Generator enabled

bit 2 (RNG)

Random Number Generator

bit 1 (AIS-E)

Alternate Instruction Set enabled

bit 0 (AIS)

Alternate Instruction Set

mystery level 8FFF_FFFEh

input

EAX=8FFF_FFFEh

unknown ^#1

output

EAX

0049_4544h

DEI

EBX

0000_0000h

reserved

ECX

0000_0000h

reserved

EDX

0000_0000h

reserved

note

description

#1

This level is only supported by the AMD K6 processor family.

mystery level 8FFF_FFFFh

input

EAX=8FFF_FFFFh

unknown ^#1

output

EAX
EBX
ECX
EDX

string

NexGenerationAMD (K6)
IT'S HAMMER TIME (K8)
HELLO KITTY! ^-^ (KB)

note

description

#1

This level is only supported by the indicated processor families.

AMD SimNow! level BACC_D00Ah

input

EAX=BACC_D00Ah

backdoor call ^#1

EDI=CA11_xxxxh

function number

EBX=xxxx_xxxxh

1st argument

ECX=xxxx_xxxxh

2nd argument

EDX=xxxx_xxxxh

3rd argument

output

EAX=xxxx_xxxxh

return value

note

description

#1

This level is only supported by the AMD SimNow! simulator.

all other levels

input

EAX=xxxx_xxxxh

desired CPUID level

output

EAX=xxxx_xxxxh
EBX=xxxx_xxxxh
ECX=xxxx_xxxxh
EDX=xxxx_xxxxh

undefined